低功率之兩階段多位元正反器聚集方法

Two-Stage Multi-bit Flip-Flop Clustering for Low Power

許筑涵(Chu-Han Hsu)

指導教授 ： 黃世旭

中原大學/電機資訊學院/電子工程研究所/碩士(2018年)

https://doi.org/10.6840/cycu201800767

摘要

現今科技的進步，電器用品越來越要求良好的工作效能，加速晶片運行速度是現在電路設計中很重要的議題。而電路中存在時序差異(clock skew)常被視為要改善的一部分，為了避免因為存在時序差異而導致電路無法運行，我們利用電路中暫存器之間的時序差異完成了降低晶片運作週期的工作。
另外，隨著積體電路設計規模成長為系統晶片(System-on-Chip)等級，一個晶片上含有的電晶體數量呈指數性成長，電路中含有大量元件帶來極大的功率消耗，如何有效降低功率消耗是一個被廣泛探討且需要被納入考量的問題，此篇論文中，我們提出了一個有效的低功率之兩階段多位元正反器聚集方法，不僅考慮了如何降低運作週期，並且將單一正反器合併成多位元正反器，以達到降低功率消耗的目的。

關鍵字

時序差異 ； 多位元正反器 ； 功率消耗

並列摘要

As the advancement of modern technology, electronic products highly require good performance. Accelerate the execution speed of a chip design is a very important issue. The utilization of clock skew in the circuit can be seen as a part of the improvement. In order to avoid the circuit being inoperable because of the clock skew, in this thesis, we make use the clock skew between the flip-flops in the circuit by completing the required operation under timing constraints.
In addition, as the scale of the integrated circuit design grows to the system on chip, the number of transistors contained on one wafer grows exponentially, and the circuit contains a large number of components, which brings great power consumption. How to effectively reduce power consumption is also a problem that is widely discussed and needs to be taken into account. Therefore, in this thesis, we propose an effective Two-Stage Multi-Bit Flip-Flop Clustering for Low Power method, which not only considers how to reduce the cycle time, but also combines flip-flops into a multi-bit flip-flop for the purpose of reducing power consumption.

並列關鍵字

Clock skew ； Multi-bit flip-flops ； Power consumption

參考文獻

第六章 參考文獻

[1] L. Bolzani, A. Calimera, A. Macii, E. Macii, M. Poncino, "Enabling Concurrent Clock and Power Gating in an Industrial Design Flow," Automation & Test in Europe Conference & Exhibition, 2009.

[2] S. K. Teng, N. Soin, "Low Power Clock Gates Optimization For Clock Tree Distribution, " 11th International Symposium on Quality Electronic Design (ISQED), 2010.

[3] K. Wang and M. Marek-Sadowska, “Buffer sizing for clock power minimization subject to general skew constraints,” in Proceedings of ACM/IEEE Design Automation Conference, 2004, pp. 159–164.

[4] J. G. Xi and W. W.-M. Dai, “Buffer insertion and sizing under process variations for low power clock distribution,” in Proceedings of ACM/IEEE Design Automation Conference, 1995, pp. 491–496.