利用多重位元正反器降低時脈功率

Clock Power Reduction Using Multi-bit Flip-Flops

張宗顏(Tsung-Yen Chang)

指導教授 ： 謝財明

中原大學/工學院/資訊工程研究所/碩士(2011年)

https://doi.org/10.6840/cycu201100586

摘要

在動態功率消耗中，時脈的功率一直是主要的消耗來源，因此減少時脈功率消耗成為一個重要的課題。近年來業界則提出新型態的正反器，稱為多重位元正反器，由於多重位元正反器的單位功率消耗與面積小於單一位元正反器，因此使用多重位元正反器取代多個單一位元正反器，可以有效的減少正反器所使用的功率消耗，同時可以減少整體正反器個數與正反器所佔面積。本篇論文提出將多個單一位元正反器合併為多重位元正反器的方法，達到減少整體正反器功率消耗的目的，同時符合時序限制和擺放正反器的面積限制。
本論文將單一位元正反器合併關係建立成merging graph，並且提出快速建立graph的方法，減少程式執行時間。接著定義Essential Prime Cover在graph之中搜尋出特定優先合併的正反器群組。在合併過程中，利用單一位元正反器合併對象的限制與可擺放區域的範圍作為合併的依據，儘可能合併出較多的多位元正反器，改善整體的功率消耗。從實驗結果得知，在業界所提供的測試數據，本論文平均降低整體功率消耗至78.07%，正反器個數降低75%，面積部份平均則減少3.75%的正反器所佔面積，顯示本論文所提出的方法是非常有效的。

關鍵字

時脈功率 ； 多重位元正反器 ； 低電壓設計

並列摘要

In the dynamic power consumption, the clock power consumption is accounted for a large number of ratio, thus reducing the clock power consumption has become an important issue. We propose a method using multi-bit flip-flops for clock power saving. The advantages of merging single-bit flip-flops to multi-bit flip-flops not only reduce the total area of integrated circuit, but also decrease the clock network power consumption and total number of flip-flop. To acquire these advantages, the design must be guaranteed to satisfy timing constraint and placement density constraint in the merging process.
We present a fast approach of merging graph construction and we define Essential Prime Cover to determine which flip-flop should be merged eailier. According to Essential Prime Cover, we can obtain more multi-bit flip-flops to improve power consumption. The experimental results show that our proposed approach reduces 22% of the power consumption on the average. Meanwhile, the number of flip-flops and the total area of circuit reduced 75%, 3.75% on the average. Therefore, our approach is very effective and efficient.

並列關鍵字

Clock Power ； Multi-bit Flip-Flops ； Low Power

參考文獻

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