正反器分群控制之低功率轉態障礙測試圖樣

Flip-Flop Grouping and Controlling for Low Power Test Patterns of Transition Delay Faults

呂承韋(Cherng-Wei Leu)

指導教授 ： 梁新聰

中原大學/工學院/電子工程研究所/碩士(2014年)

https://doi.org/10.6840/cycu201400499

摘要

在本研究中，我們建立轉態延遲障礙(transition delay fault, TDF)的低功率測試圖樣產生方式。令V1及V2訊號中屬於正反器的值，盡可能保持不變，測試較多的TDF障礙，達到低功率之測試過程。在LOC測試架構下，為了使大部份正反器不須進行投值(launch)動作，我們分析電路虛輸入(pseudo primary input, PPI)可能影響的最小區域，將電路修改為暫時電路，尋找一些固定PPI值的訊號組合，將PPI設下固定值送入ATPG軟體產生測試圖樣，這些只讓PI轉態的測試圖樣可以測得將近一半的TDF障礙，剩餘的障礙，我們藉由分析電路裡正反器之間的關係將正反器做分群，參考分群資訊將電路修改為每次只保留一群正反器的暫時電路，利用先前建立的固定PPI值訊號組合，將暫時電路的PPI值固定住，產生只讓部分正反器進行投值的測試圖樣，最後針對剩下的障礙我們讓全部正反器可以自由投值產生出測試圖樣，即組成我們的低功率測試圖樣。

關鍵字

轉態延遲障礙 ； 低功率測試 ； 正反器排序

並列摘要

In this thesis, we propose a method of generating low-power test patterns for transition delay faults(TDF). We make the values of flip-flops for V1 and V2 be fixed as much as possible to detect more TDF, achieving the purpose of low power testing.
For LOC test application, to make most flip-flops need no launch operations, we analyze the minimum area affected by pseudo primary inputs (PPI). Accordingly we modify circuits temporarily for searching combinations of fixed PPI. Then we set the fixed values on PPI and use ATPG to generate test patterns. These patterns, only changing values on PIs, can detect nearly a half of TDF.
For the remaining faults, we analyze circuit structure to find the relationship between flip-flops and grouping flip-flops by referring to the relationship. We then modify circuits with only a group of flip-flops left for scan flip-flops and the other groups be stuck with found fixed values for PPI. Accordingly we can generate test patterns with only a group of flip-flops doing launch operation.
Finally, for the remaining faults, we apply general LOC test generation method to search patterns. This complete our work of searching low-power test patterns.

並列關鍵字

transition delay fault ； low power testing ； flip-flop order

參考文獻

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“Power Driven Chaining of Flip-flops in Scan Architectures,” in Proc. IEEE Intn’l Test Conf., pp. 796-803, 2002.

[2]Meng-Fan Wu, Kai-Shun Hu, and Jiun-Lang Huang, “An Efficient Peak Power Reduction Technique for Scan Testing,” in Proc. 16th Asian Test Symp., pp.111-114, 2007.

[3]Xiaoqing Wen, “Towards the Next Generation of Low-Power Test Technologies,” in Proc. IEEE 9th Intn’l ASIC Conf. (ASICON), pp. 232 – 235 , 2011.

[4]W. Lee, “Adapting scan architectures for low power operation,” in Proc. IEEE Intn’l Test Conf., pp. 863-872, 2000.