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  • 學位論文

建立正反器三群分割位移時投值之低功率測試圖樣

Generating Low-Power LOS Patterns for Three-Group Flip-Flop Partitions

指導教授 : 梁新聰

摘要


本文中,我們改善了利用分二群正反器LOS測試轉態延遲障礙(transition delay fault, TDF)的方法,建立正反器分三群LOS產生低功率測試圖樣的方式。我們將分兩群正反器的方法改為分三群,好處是原本分兩群我們只能控制一半的正反器不投值及抓值,分三群能控制過半數的正反器不投值及抓值,可降低測試功率及增加障礙含蓋率。由於將分兩群的分群方式用於分三群電路時,會產生因為群數不同,導致最末群的正反器數量多於其他群正反器,造成位移功率不平均等等的問題,所以我們將分群方式改善以利我們做分三群LOS的測試方式。在使用部分正反器固定值組合尋找測試圖樣時,我們改變方法,原本是將正反器完全固定住,這種方法可能會產生很多的測試信號,我們則將正反器don’t care值留住,利用此法尋找測試圖樣。最後用這些修改的方法產生低功率測試圖樣。

關鍵字

低功率測試

並列摘要


In this thesis, we propose a method of generating low-power los patterns for three-group flip-flop partitions to test transition delay faults (TDF). The method is an improvement of the original two-group flip-flop partitions method to three-group flip-flop partitions. Three-group flip-flop partitions method can control more than a half of flip-flops to not launch or capture values. This reduces test power and improves fault coverage. We find some problems of two-group flip-flop partitions method when applying to three-group flip-flop partitions method, e.g. last group may have more flip-flops than other groups. This induces not average in shift power for three groups of flip-flops. So, we revise the method of grouping flip-flops when partitioning flip-flops into three groups. In addition, we change the method of using fixed ppi values to search patterns. Instead of giving fixed values on don’t care values, we remain don’t care values on ppi to generate test patterns. These revised methods help us generate low-power test patterns at last.

並列關鍵字

Low-Power LOS

參考文獻


[1]許翊筠,“多段多串設計之低功率位移末投值測試圖樣”,中原大學 碩士論文,2016.
[10]呂承偉, “正反器分群控制之低功率轉態障礙測試圖樣”,中原大學碩士論文,2014.
[2] Ozgur Sinanoglu, “Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing,” in Proc. IEEE Asian test Symposium, pp. 20-23, Nov. 2011.
[4]G. Xu and A. D. Singh, “Low Cost Launch-on-Shift Delay Test with Slow Scan Enable”, in Proc. IEEE European Test Symp., pp. 9-14, 2006
[5]N. Ahmed, C.P. Ravikumar, M. Tehranipoor and J. Plusquellic, “At Speed Transition Fault Testing with Low Speed Scan Enable”, in Proc. IEEE VLSI Test Symp., pp. 42-47, 2005.

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