多段多串設計之低功率位移末投值測試圖樣

Low Power Launch-off-Shift Test Patterns for Multi-Segment Multi-Segment Multi-Chain Design

許翊筠(YI-YUN HSU)

指導教授 ： 梁新聰

中原大學/電機資訊學院/電子工程研究所/碩士(2016年)

https://doi.org/10.6840/cycu201600049

摘要

在本研究中，我們為轉態延遲障礙(transition delay fault, TDF)，建立可以多串多段進行測試的低功率LOS (launch-off-shift)測試圖樣產生方式。我們分析電路的主要輸入(Primary Inputs, PI)或假輸入(Pseudo Primary Inputs, PPI)各自影響範圍，以減少電路輸入的轉態次數為目標，準備出可以降低電路測試功率的測試圖樣。我們分工作為三部份，首先我們分析PPI可能影響的最小範圍，將電路修改為暫時電路，建立FixPPI組合，然後使用ATPG軟體產生測試圖樣，這些PI轉態但PPI為固定值的測試圖樣，可以測得將近一半的TDF障礙，第二部分則針對剩下障礙，我們藉由電路裡正反器之間關係將正反器做分群，運用分群資訊，修改電路為只保留一群正反器的暫時電路，使另一群正反器PPI的V1及V2值，盡可能保持不變，建立只有一群正反器投值(Launch)時會改變值的LOS測試圖樣，最後再針對剩下的障礙，讓全部正反器可以自由投值，產生測試圖樣，以上三部分的測試圖樣即組成我們的低功率測試圖樣。對於ISCAS89標準電路，平均而言，我們在投值功率降低了43.85%，而抓值功率降低了30.61%。

關鍵字

低功率測試 ； LOS

並列摘要

In this thesis, we propose a method of generating low-power launch-off-shift test patterns for transition delay faults (TDF) in designs using multi-segment multi-chain architecture. We analyze the circuit part affected by primary inputs (PI) and pseudo primary inputs (PPI). Then we prepare patterns for low power testing, which target on reducing transitions on PPIs and inside circuits. There are three parts in our work. First, we analyze the minimum circuit area possibly influenced by PPI. We modify the circuit under test to temporary circuits and generate FixPPI values accordingly. Then we use ATPG to search patterns for TDF faults. These patterns can detect almost a half of total TDF. Second, for the rest of faults, we analyze circuit structure to find the relationship between flip-flops and use the relationship to distribute flip-flops into groups. We modify the circuit under test to two temporary circuits, each of which has one group of flip-flops be chained in a scan chain and the other group be stuck on fixed values found by our algorithm. Accordingly, we can generate LOS test patterns with only a group of flip-flops doing launch operation. Finally, for the remaining faults, we generate general LOS test patterns that have no restriction on launch operation. The aforementioned three parts of patterns compose the complete set of our low power LOS test patterns. Experiments on ISCAS89 and ADDENDUM93 benchmark circuits show that our patterns can reduce in average 43.85% for launch power and 30.61% for capture power.

並列關鍵字

low power ； LOS

參考文獻

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