產生低功率投值後抓值測試圖樣之新型流程設計

此篇論文中，我們提供了一種新的方法，對轉態延遲障礙(transition delay fault, TDF)產生低功率的LOC(launch off capture)測試圖樣，而這些測試圖樣，都具有部分正反器在進行投值(launch)與抓值(capture)的時候，能夠保持固定值，達到低功率測試的效果。我們改善之前的複雜程序，直接修正部分正反器，使其輸出連結到正反器原有的輸入端，成為暫時電路，再使用自動測試圖樣產生(automatic test pattern generation, ATPG)軟體，即可產生部分正反器不需改變值，卻能測到TDF的測試圖樣，這些圖樣將可以降低許多測試功率。

關鍵字

低功率測試；轉態延遲障礙

並列摘要

In this thesis, we propose a method of generating low-power launch-off-capture test patterns for transition delay fault. Each pattern only needs a part of flip-flops to change value during launch cycle and capture cycle, therefore being able to reduce test power dissipation. Instead of using complex procedures for searching patterns, we directly modify only a group of scan flip-flops by connecting their outputs to their original inputs, respectively. These temporary circuits are used in an automatic test pattern generation tool to search patterns. The obtained patterns can make only a part of flip-flops change values during test for transition delay faults and reduce much test power accordingly.

並列關鍵字

low power testing ； LOC ； transition delay fault

參考文獻

[6] 許翊筠，為多段多串設計之低功率位移末投值測試圖樣，中原大學電子工程學系論文，105年1月.

[10] 呂承韋，正反器分群控制之低功率轉態障礙測試圖樣，中原大學

[1] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press,1994 (revised printing).

[4] J. Savir, “Skew-Load Transition Test: Part I, Calculus,” in Proc. IEEE Intn’l Test Conf., pp. 705-713, 1992.

[5] L. Whetsel, “Adapting scan architectures for low power operation,” in IEEE International Test Conference (ITC 2000), October 2000, pp. 863–872.

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產生低功率投值後抓值測試圖樣之新型流程設計

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