低功率多掃描串之轉態延遲障礙測試設計

Low Power Testing with Multiple Scan Chains for Transition Delay Faults

詹前佑(Qizn-You Zhan)

指導教授 ： 梁新聰

中原大學/工學院/電子工程研究所/碩士(2013年)

https://doi.org/10.6840/CYCU.2013.00162

摘要

在此研究中，我們建立一種低功率的轉態延遲障礙(Transition Delay Fault, TDF)測試圖樣產生方式以及配合進行測試之控制電路。TDF測試圖樣會在電路的主要輸入(Primary Inputs, PI)或假輸入(Pseudo Primary Inputs, PPI)發生轉態，減少這些轉態的次數可以降低電路的測試功率。因此我們分析PPI可影響的範圍，尋找PPI的訊號組合，以這些組合修改電路為暫時電路，然後將這些暫時電路送入ATPG軟體產生測試圖樣，這些PI有轉態但PPI為固定值之測試圖樣，可以測得接近一半的TDF障礙，剩下的障礙再為其產生PPI有轉態的圖樣。接著我們分析PPI有轉態的圖樣，配合多掃描串(Multiple Scan Chains)測試架構，建立大部分圖樣只須一串正反器進行位移(Shift)、投值(Launch)及抓值(Capture)的動作，並決定分串方法，少部分圖樣仍然需要全部掃描串有動作，我們設計的控制電路，也能配合控制多掃描串測試架構，達到低功率的測試效果。

關鍵字

轉態延遲障礙 ； 低功率測試圖樣 ； 投值操作

並列摘要

In this paper, we propose a method to generate low power test patterns for testing transition delay fault(TDF). TDF test patterns will transitions occur in the circuit primary inputs(PI) and pseudo primary inputs(PPI).Reducing the number of these transitions can obtain lower power. We analyzed the maximum area of circuits possibly not influenced by PPI, looking for these PPI signal combinations. These PPI combinations are used to construct temporary circuits for test generation. These patterns freeze clocks for all flip-flops during launch operations and can detect almost a half of total TDF faults. Then we analyzed pattern have transitions on PPI, with multiple scan chain test architecture. I hope every pattern can shift, launch and capture data by only one scan chain. If the two scan chains of small part pattern needed active, can also apply to this multiple scan chain test architecture, this pattern does not to be removed. Reached the effect of power reduction, and Fault Coverage not reduce.

並列關鍵字

low power test patterns ； launch operation ； transition delay fault

參考文獻

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