為多段多串設計建立低功率投值後抓值 之測試圖樣

Low Power Launch-off-Capture Test Pattern Generation for Multi-Segment Multi-Chain Design

羅光益(Kuang-Yi Lo)

指導教授 ： 梁新聰

中原大學/電機資訊學院/電子工程研究所/碩士(2016年)

https://doi.org/10.6840/cycu201600454

摘要

在此研究中，我們建立一個低功率的轉態延遲障礙 (transition
delay fault, TDF) 測試圖樣產生方法，使得測試圖樣 V1 及 V2 訊號中屬於正反器的部份值可以盡可能保持不變，並測得最多的 TDF 障
礙，以達成低功率之測試過程。在使用 LOC(launch off capture)測
試架構下，為了使大部份正反器不須進行投值(launch)動作，我們將
正反器拆解成假輸入(Pseudo Primary Inputs, PPI)與假輸出
(Pseudo Primary Outputs, PPO)，成為暫時電路，我們分析電路的
主要輸入(Primary Inputs, PI)與 PPI 各自影響範圍，並找出電路
PPI 可能影響的最小區域，進而尋找一些 PPI 的訊號組合。
使用自動測試圖樣產生(automatic test pattern generation,
ATPG)軟體並配合 PPI 組合，產生 TDF 測試圖樣，這些圖樣的變化位
置，都發生在 PI 上，而這些測試圖樣可以測得接近一半的 TDF，卻完
全不需要正反器進行投值動作，我們稱做 Non-Launch patterns。
剩餘未經 Non-Launch patterns 測得的障礙，我們將依據 strongly
connected components (SCCs)進行 scan chain 的分串，並試著利用部分 PPI 固定的方法繼續找出部分正反器不需投值的 LOC 測試信號，我們稱做 Part-Launch patterns。
最後剩餘的障礙，我們建立單串掃瞄串可以測試這些障礙的測試圖
樣，也就是我們不限制正反器的投值動作。所有這些測試圖樣可以測
得更多的 TDF 障礙，而最後我們分析所有測試圖樣傳出障礙的位置，
將測試信號分類，並分析所有測試圖樣的測試功率，包括投值與抓值
功率，證明所得測試圖樣可以達到降低功率的目標。

關鍵字

低功率測試 ； LOC

並列摘要

In this thesis, we construct a method to generate low power test patterns
for transition delay faults (TDF). We try to hold the values of most flipflops in the initialization and propagation steps of patterns for testing TDF.
These patterns can be used to freeze the flop-flops during launch cycles
and/or capture cycles for launch-off-capture (LOC) test application. We
search the maximum area of circuits possibly not influenced by the
changing values of flip-flops. From this we build a temporary circuit in
which we change flip-flops to pseudo primary inputs (PPI) and pseudo
primary outputs (PPO) and set required stuck values on PPI. The values are
called stuck PPI combinations. They are used to construct temporary
circuits for test generation. The target TDF faults belong to the circuit area
possibly not influenced by the changing values of flip-flops. We can then
obtain test patterns that have only changing values on primary inputs
during launch operations. These patterns can in average detect almost a
half of total TDF faults for a circuit. We call these patterns Non-Launch
patterns.
For the remaining faults, we distribute flip-flops into two groups based
on strongly connected components (SCCs) and keep using the stuck PPI
combinations to find patterns for which a group of flip-flops need not
launch. We call these patterns Part-Launch patterns. For the remaining
faults, we generate test patterns for single chain for them. These three kinds
of patterns can achieve higher fault coverage. In addition, for each of the
obtained patterns, we analyze the detected faults and where they can be
propagated to classify the patterns. The patterns are rearranged to lowpower test patterns at last. We analyze the launch power and capture power
of all patterns and show that they can achieve the purpose of reducing test
power.

並列關鍵字

low power testing ； LOC

參考文獻

[8] 詹前佑，低功率多掃描串之轉態延遲障礙測試設計，中原大學電

[9] 呂承韋，正反器分群控制之低功率轉態障礙測試圖樣，中原大

Capture Power Reductionin Launch-Off-Capture Testing,” in Proc.

[2] H.-C. Liang and C.-J. Ho, “Multi-function Controller for Low-Power

Multiple Scan Test of Transition Delay Faults,” IEEE The 3rd Intn’l