低功率多掃瞄串測試之正反器分串方法

Chain Decision for Low-Power Multiple Scan Testing

李承翰(Cherng-Hann Lee)

指導教授 ： 梁新聰

中原大學/工學院/電子工程研究所/碩士(2012年)

https://doi.org/10.6840/cycu201200597

摘要

在此研究中，我們提出一種低功率多掃瞄串測試的正反器分串方法，以測試轉態延遲障礙(transition delay fault, TDF)。我們分析Launch-off-capture(LOC)測試圖樣，以配合多掃瞄串測試架構中，每組圖樣只有位移一串正反器資料，並使用一串正反器進行投值(launch)及抓值(capture)之要求，決定正反器之分串方法。我們為原本測試固值障礙(stuck-at fault)的多掃瞄串分串方法，加入測試圖樣轉態位元(transition bit)數量之考量，分析TDF測試圖樣，以便將正反器分串。在此種設計中，每組測試圖樣有其安排之驅動掃描串(active scan chain)及匹配掃描串(match scan chain)，可以達成低功率之測試過程。目前已完成部份ISCAS’89電路之實驗，顯示此方法之可行性。未來我們將分析所安排圖樣在測試過程中可以達到的低功率效果，以及將方法應用至較大型之ISCAS’89電路。

關鍵字

轉態延遲障礙 ； 低功率測試 ； 多掃描串測試

並列摘要

In this paper, we propose a method of chain decision for low-power multiple scan chain testing on transition delay faults (TDF). We generated and analyzed the patterns of launch-off-capture (LOC) testing for TDF. These patterns are designed for the multiple scan testing framework, in which each pattern need to shift, launch, and capture data on only one scan chain. Accordingly the flip-flops are selected into separate groups. We revised a previous multiple scan chain division method for stuck-at faults testing with additional consideration of transition bits between the first and second patterns of TDFs. In this method, each pattern produces one active scan chain only, therefore making low-power LOC testing be possible. Currently we have experimented on a part of ISCAS98 circuits to prove the feasibility of proposed method. In the future we will analyze the effect of power reduction on testing, and apply the method to larger ISCAS98 circuits.

並列關鍵字

transition delay fault ； Multiple Scan Chain Testing ； Low-power Testing

參考文獻

[1] Z. You, J. Huang, M. Inoue, J. Kuang, and H. Fujiwara, “Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power”, 19th IEEE Asian Test Symposium, pp.371-374, 2010.

[2] Z. You, T. Iwagaki, M. Inoue, and H. Fujiwara, “A Low Power Deterministic Test Using Scan Chain Disable Technique”, IEICE Trans. Inf. & Syst., Vol.E89-D, No.6, June 2006.

[3] Lee Whetsel, "Adapting Scan Architectures for Low Power Operation," in Proc. Intn'l Test Conf., paper 33.1, pp.863-872, 2000.

[4] N. Nicolici and B. M. Al-Hashimi, "Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits," IEEE Trans. on Computers, Vol. 51, No. 6, pp.721-734, June 2002.

[5] P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, "Scan Architecture for Shift and Capture Cycle Power Reduction," in Proc. of the 17th IEEE Intn'l Symp. on Defect and Fault Tolerance in VLSI Systems, 9 pages, 2002.