Effective LFSR Reseeding Technique for Achieving Reduced Test Pattern

S. Saravanan ； Har Narayan Upadhyay

《Research Journal of Applied Sciences, Engineering and Technology》 4卷22期 (2012/11) Pp. 4783-4786

並列摘要

Aim of this study is to focus on reducing test pattern with effective Linear Feedback Shift Register (LFSR) reseeding. Test data volume of modern devices for testing increases rapidly corresponding to the size and complexity of the Systems-on-Chip (SoC). LFSR is a good pseudorandom pattern generator, which generates all possible test vectors with the help of the tap sequence. It can achieve high fault coverage by reducing correlation between the test vectors. Reseeding is a powerful method for reducing the test data volume and storage. This study presents a new LFSR reseeding technique for efficient reduction of test pattern. A new encoding technique is proposed in this study which is used to reduce the size of the test data. Size of the test data can be reduced by LFSR clock which is inactive for several clock cycles after the input seed is given. When the clock goes to inactive state, a rotate right shift operation is done on the seed to get all the remaining possible values. After getting all the possible values for that seed a new seed is given by making the clock active. Test data volume is reduced by storing the data only when the clock is active. With in the reduced clocks, rest of all the remaining test vectors was derived. A special Control logic is used to make the clock active as well as inactive. Experimental results are targeted to ISCAS89 benchmark circuits.

並列關鍵字

Clock active and inactive ； control logic ； encoding ； linear feedback shift register reseeding