用於降低平均電壓降之測試向量修改

Test Pattern Modification for Average IR-drop Reduction

丁瑋陞(Wei-Sheng Ding)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.02391

摘要

本論文提出一個新穎的想法去修改測試向量為了減少在捕獲週期時間平均的電壓降。我們提出了一個快速的平均電壓降的估計，它和耗時的暫態電壓降分析結果非常相近(R2 =0.99)。我們計算每一個節點對於在電壓降熱點中節點的貢獻量為了我們可以僅僅修改一點點部分有效地修改測試向量去降低電壓降。實驗結果顯示我們的技術成功的降低時間平均電壓降達10%，並且幾乎沒有任何的錯誤涵蓋率的下降，也幾乎沒有任何測試向量的膨脹。我們提出的技術相對於考慮功率的自動測試向量產生器有較短的測試向量、較低的電壓降、較高的錯誤涵蓋率。

關鍵字

電壓降 ； 測試向量修改 ； 低功率測試

並列摘要

This thesis presents a novel technique that modifies ATPG test patterns to reduce time-averaged IR drop of a test pattern in capture cycles. We propose a FAIR estimation, which is very close to the time-averaged IR drop of time-consuming transient simulation (R2 =0.99). We calculate the contribution of every node to these nodes inside IR-drop hotspot so that we can effectively modify only a few don’t care bits in the test patterns to reduce IR drop. Experimental results show that our technique successively reduce time-averaged IR drop by 10% with almost no fault coverage loss and no test inflation. The proposed technique generates shorter test sets with lower IR drop and higher fault coverage than commercial power-aware ATPG.

並列關鍵字

IR drop ； test pattern modification ； low-power testing

參考文獻

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