基礎於測試向量重新排序之方法改良以降低電路測試期間之功率消耗

Power Reduction for Circuit Under Testing Based on Test Vector Reordering

蔡佳青(Chia-Ching Tsai)

指導教授 ： 曾王道

元智大學/資訊學院/資訊工程學系/碩士(2006年)

https://doi.org/10.6838/YZU.2006.00239

摘要

由於科技發展迅速，超大型積體電路的設計發展與製造技術在最近幾年中成長更為快速，擁有高效能與高密度整合電路的研發是業界相同目標，相對的使得晶片整體複雜度增加。因此，測試時間與功率消耗的增減，將影響整個生產成本。在本論文中，我們將針對整合電路(Combination Circuit)在測試時的功率消耗問題，提出一個優化的改良技術。整個論文的技術核心在於減少整合電路內部信號(signal)的轉換次數(Transition Count)，以達到降低功率消耗的目的。而此技術的主要觀念是利用任意兩組輸入測試向量(Test Vector)之間，每一個相關信號位元前後的差異轉換次數，進而重新編排輸入測試向量的順序來達成研究的目標。我們提出四個步驟來解決這些問題。首先考慮整合電路內部各邏輯閘的轉換機率，表示每個輸入信號對內部造成影響的程度；緊接著分別計算所有相關測試向量間，主要輸入與掃描輸入兩部分的差異轉換次數，由上述兩個步驟我們可獲得各組測試向量間的總轉換次數並賦予不同的權重值(weight)，依此建構一個有向圖，並使用貪婪演算法求取最適的測試向量編排順序。綜合上述，我們選取標準的受測整合電路來進行驗證，並將測試向量組中未考慮到掃描輸入部分的相關論文建立實驗對照組，由最後的實驗結果得知，將比對照實驗組有效降低電路內部轉換次數。因此，本論文提出的方法將有效降低整合電路的消耗功率。

關鍵字

測試向量重新排序

並列摘要

As the development in science and technology is fast, the design and manufacturing technology of the Very Large-Scale Integrated circuit (VLSI) is developed and grown up faster during recent years. It is the same goal of industry to achieve the research and development of the high performance and density of combination circuit. Ironically, the chip is getting more complex. Therefore, the amount of test time and power consumption will influence the whole production cost. In this thesis, we will put forward an optimized technology for improvement of power consumption of Combination Circuit while testing. The main technology of this thesis is decreasing the number of internal signal transition counts so as to reduce the power consumption. And the main idea of this technology is using the difference of number of conversion of every relevant signal location of two inputs Test Vector wantonly, and then rearranges the vector order to reach the goal studied. We propose four steps to solve this problem. First of all, we shall consider the probability of transfer of internal gates of combination circuit. It indicates the internal influence of each input signal. Then, calculates the difference of number of conversion of main and scan input. Following the two steps, we can get the total transfer counts of each group of vectors under test and give it different weight. Base on this to construct a vector figure, and then using greedy algorithm to secure the optimized arrangement of test vectors. Conclusively, we select standard combination circuit to verify this technology. So, the method that this thesis puts forward will reduce effectively the power consumption of the combination circuit.

並列關鍵字

Test Vector Reordering

參考文獻

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