A Tunable Low-Power Semi-Digital Interface Circuit for Capacitive Sensors with Calibration Procedure

A new technique and circuit topology is proposed to read the output of a capacitive sensor for lab-on-chip (LOC) applications. Through capacitance-to-time conversion, together with several digital blocks, a first-order sigma-delta interface is developed. By encoding the change in capacitance as the difference in time between the rising edges of two digital signals, a compact, low-power realization is achieved. Moreover, the design is tunable along three axes: power, resolution and range. A digital calibration procedure is provided that exploits these three degrees of tuning and enables the design to be optimized for a desired capacitance range. A circuit has been fabricated in a 1-V 90-nm ST CMOS process requiring 120 μmx20 μm footprint. Tests were conducted with on-chip capacitance ranging from 12.5 fF to 8 pF and the circuit was shown to be capable of measuring this full range of capacitance in a piecewise manner with a power consumption of 34 μW.

並列關鍵字

Capacitive Sensors ； Interface ； Digital ； Low-power ； Calibration

國際替代計量

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