低電源雜訊之電流/電壓轉換線性穩壓積體電路研製

Design and Implementation of Low Power-Bounce Current-to-Voltage-Conversion Dropout Linear Regulator Integrated Circuits

李新通(Hsin-Tung Li)

指導教授 ： 陳建中

國立臺北科技大學/電資學院/電子電腦與通訊產業研發碩士專班/碩士(2007年)

摘要

隨著電子科技的發達，積體電路科技越來越廣受青睞，尤其是在VLSI電路與嵌入式系統及類比、數位積體電路設計方面，現在積體電路製程技術的成熟，進而可將多個電路合成單一個積體化，使我們的電路功能愈來愈齊全，但在電路與電源之間會有一些線路電感、電阻…等所產生的雜散效應，我們稱之為power bounces和 ground bounces [1-2]，如果此雜散效應過大可能會使電路產生誤動作及輸出結果的不正確，尤其在數位類比混合更是影響盛大，因此我們利用此論文電路架構來改善其雜散效應，並再加以應用組成低壓降穩壓器電路，與一般低壓降穩壓器做比較並觀察其結果是否有改善原先不理想的地方。
本論文主要目的為利用單一米勒補償電容在內的低電源雜訊來設計一新型電流/電壓轉換線性穩壓積體電路，藉由使用電流/電壓轉換線性穩壓積體電路去抑制高電源雜訊。此電路已由TSMC 0.35μm 2P4M CMOS製程實現，晶片面積226μm x310μm。當輸出電容為1μF的電解電容，且輸出電壓在0.5%的誤差範圍時，所測得的滿載輸出電壓穩定時間為400ns。此外，這電源調節率和負載調節率分別是14μV/mA和4.44ppm/mA表示。輸出電流為150mA時，輸入輸出電流差(dropout current)為1.0741mA。在152mA電源電流下，測量電流效率99.4168%。

關鍵字

低壓降線性穩壓器 ； 低電源雜訊 ； 等效串聯電阻

並列摘要

With the development of electronic technology, the integrated circuits is more and more widely favored, especially in VLSI circuit, embedded system, and analog and digital IC deign. By the maturity of a technology that the integrated circuit at present time, we can integrate different circuits into a single chip, and make the function of our circuit to be more completed, but there are some stray inductances and resistances between circuits and power supply which could product glitches. We call the power bounces and ground bounces [1-2]. If this stray effect is too large, it is possible to make mistake and the result of output may be incorrect. It influence grandly in mixed-signal circuit, so the purpose of this circuit is to reduce power bounce which is produced by stray components. We compare other general LDO, and observe the result.
A novel Low Power-Bounce Current-to-Voltage-Conversion Dropout Linear Regulator Integrated Circuits with single Miller compensation capacitor is presented. By utilizing the current mode architecture to suppress power bounce. The proposed Current-to-Voltage-Conversion Dropout Linear Regulator Integrated Circuits have been fabricated in TSMC 0.35μm 2P4M CMOS technology. The measurement results show the settling time which can achieve 400ns with 0.5% error for full load-current. Furthermore, the line and load regulations are 14μV/mA and 4.44ppm/mA, respectively. The dropout current is 1.0741mA for 150mA output current. The measured current efficiency is 99.4168% in 152mA supply current. The active chip area is 226μm x310μm.

並列關鍵字

low-dropout linear regulator ； low power-bounce ； equivalent series resistance

參考文獻

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