Designing Interconnection Networks for Multi-level Packaging

M. T. RAGHUNATH ； ABHIRAM RANADE

《VLSI Design》 1995卷 (1995/12) Pp. h375-388

https://doi.org/10.1155/1995/57617

摘要

A central problem in building large scale parallel machines is the design of the interconnection network. Interconnection network design is largely constrained by packaging technology. We start with a generic set of packaging restrictions and evaluate different network organizations under a random traffic model. Our results indicate that customizing the network topology to the packaging constraints is useful. Some of the general principles that arise out of this study are: 1) Making the networks denser at the lower levels of the packaging hierarchy has a significant positive impact on global communication performance, 2) It is better to organize a fixed amount of communication bandwidth as a smaller number of high bandwidth channels, 3) Providing the processors with the ability to tolerate latencies (by using multithreading) is very useful in improving performance.

關鍵字

Parallel processing ； interprocessor communication ； network topology ； packaging hierarchy