Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures

AUSIF MAHMOOD

《VLSI Design》 1996卷 (1996/12) Pp. 59-68

https://doi.org/10.1155/1996/91035

摘要

The development of multi-processor architectures requires extensive behavioral simulations to verify the correctness of design and to evaluate its performance. A high level language can provide maximum flexibility in this respect if the constructs for handling concurrent processes and a time mapping mechanism are added. This paper describes a novel technique for emulating hardware processes involved in a parallel architecture such that an object-oriented description of the design is maintained. The communication and synchronization between hardware processes is handled by splitting the processes into their equivalent subprograms at the entry points. The proper scheduling of these subprograms is coordinated by a timing wheel which provides a time mapping mechanism. Finally, a high level language pre-processor is proposed so that the timing wheel and the process emulation details can be made transparent to the user.

關鍵字

Simulation ； Behavioral Simulation ； Performance Evaluation ； Process Simulation ； Hardware Processes ； Parallel Architecture Simulation