Applying the I-V Method and the Dynamic Sampling to Implement Complex Impedance Measurement in A Hybrid ARM-FPGA based Platform

This paper presents the use of a novel hybrid ARM-FPGA platform to design a complex impedance measurement system with the I-V method and the dynamic sampling rate. The system uses a programmable and fully integrated direct digital synthesis (DDS) chip to generate a stable sine wave and be applied to a complex impedance measurement circuit. Two 256-point Fast Fourier Transform (FFT) Hardware Description Language (HDL) modules are implemented in the FPGA to reduce the computing burden on the ARM processor and improve its performance. The dynamic sampling technique is used to reduce the leakage effect of the FFT, which applies a 200 MHz sampling counter to dynamically and precisely adjust the sampling frequency of ADC according to the output frequency of the DDS. Finally, the ARM processor inside the FPGA reads the magnitude and phase information of voltages V1(t) and V2(t) from the 256-point FFT HDL modules, respectively, and then calculates the magnitude and phase of the Z_(DUT) based on the R_(REF).

關鍵字

impedance measurement ； I-V method ； fast fourier transform ； dynamic sampling

並列摘要

本文以混合ARM-FPGA為核心的平台採用電流電壓方法與動態取樣率，設計複數阻抗量測系統。使用可程式的數位訊號合成晶片產生穩定的正弦波，加在複數阻抗量測電路上。以FPGA實現兩個獨立的256點的快速傅立葉轉換模組，可減少ARM處理器的運算負荷，並有效提昇效能。以200 MHz的取樣計數器動態且精確地依照正弦波的輸出頻率，調整數位類比轉換器的取樣時間，動態取樣技術可減少使用快速傅立葉轉換時會產生的洩漏效應。最後以在FPGA內部的ARM處理器，分別讀取由兩個256點的快速傅立葉轉換模組，所計算出的V1（t）與V2（t）的振幅與相位。再以參考電阻計算並求出未知複數電阻的大小與相位。

並列關鍵字

阻抗量測；電流－電壓法；快速傅立葉轉換；動態取樣

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