使用標準邏輯元件及相對式參考模型技術設計之靜態電壓壓降偵測器與嵌入式矽振盪器

Design of a Static IR-Drop Monitor and An On-Chip Silicon Oscillator with Cell-Based and Relative Reference Modelling Approaches

孫美怡(Mei-I Sun)

指導教授 ： 鍾菁哲

國立中正大學/工學院/資訊工程學系/碩士(2015年)

摘要

由於現今的系統晶片整合度日益提高，對於晶片工作時的電力網路中壓降監控的重視度也更勝以往。本論文提出一個根據相對參考模型建立而成的全數位壓降監控器。 在一點1.1V電壓校正後，此全數位壓降監控器可以監控晶片的工作電壓，並且將增測到的電壓轉成數位的編碼輸出給後續系統晶片測錯和測試使用。他可以達到0.027mV的解析度且最大誤差為16.4mV在製程、電壓和溫度飄移之下。
此外，在先前利用相對參考模型建立而成的全數位震盪器也有所改進。改進了先前全數位震盪器中費時的邏輯閘選擇的過程，改以兩個可調整式的震盪器取代。利用控制兩個震盪器的控制碼來得到期望中溫度和電壓對應延遲比例的趨勢線。以上兩個研究皆是建構於相對參考模型並且在90奈米製程技術實現。

關鍵字

抵抗製成溫度電壓飄移 ； 全數位 ； 靜態電壓感測器 ； 震盪器

並列摘要

Due to the high level integration of the system-on-a-chip (SoC), it becomes more and more important to monitor the IR drop of the power network during chip operation. In this thesis, an all-digital on-chip voltage sensor which uses a relative reference modeling (RRM) is presented. After one-point calibration at 1.1V, the proposed all-digital voltage sensor can monitor the operating voltage of the chip and outputs digital codes for SoC chip debugging and testing. It achieves a 0.027mV resolution and has a maximum error 16.4mV with process, voltage, and temperature (PVT) variations.
In addition, the prior work of the on-chip oscillator with RRM is improved. The timing consuming cell selection flow in prior on-chip oscillator design can be reduced by two digital controllable oscillators. The control codes of the two DCOs are adjusted to achieve the desired trend lines of delay ratio versus temperature and voltage curve. As a result, the frequency error of the on-chip oscillator can be reduced. Both the proposed relative reference modeling based static IR-drop monitor on-chip silicon oscillator are implemented in 90nm CMOS process.

並列關鍵字

static IR-drop monitor ； all-digital ； oscillator ； tolerance PVT variations

參考文獻

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