適用於嵌入式硬體平台之色彩空間轉換器設計

A Cost-Efficient VLSI Architecture for Color Space Conversion Processors

夏至賢(Chih-Hsien Hsia) ； 孔燕(Yan Kong) ； 張智貞(Chih-Chen Chang)

《中正嶺學報》 45卷2期 (2016/11) Pp. 133-142

摘要

一般在設計色彩空間轉換器（Color Space Conversion，CSC）時，因為RGB三原色的關係在超大型積體電路（Very Large Scale Integration，VLSI）設計時會使用較多的暫存器（Register）進而產生其硬體成本的增加。有鑑於此，本研究提出了一個管線架構（Pipelining architecture）並配合摺疊架構（Folding architecture）的設計，應用於RGB轉換至YC_bC_r色彩空間；在改良架構中以管線處理的步驟，將其處理優化，並利用三原色非同步處理的特性配合摺疊架構成一組管線架構，使其具有即時性、高硬體使用率、以及低成本的特性。最後，本文使用Xilinx FPGA實現，將實際的RGB資料經由本系統做轉換並處理後的YC_bC_r值與其理論值比較，得到較低的誤差平均值為Y＝0.231％、C_b＝0.221％、C_r＝0.149％、減少暫存器使用量為36.59％以及減少邏輯元件的使用量為67.57％。

關鍵字

影像色彩處理器 ； 色彩空間轉換 ； 管線架構 ； 摺疊架構

並列摘要

During general Color Space Conversion (CSC), the Red, Green, and Blue (RGB) color model in VLSI requires many registers and thus is associated with high hardware-related costs. This study proposed a folded and pipeline architectures in which RGB was converted into a YC_bC_r color space. The new design included optimized pipeline processing and independent processing of RGB channels and had higher instantaneity, hardware usage, and cost-efficiency. Finally, Xilinx FPGA was used to compare the actual RGB data and the converted and processed YC_bC_r values and theoretical values. The errors obtained were minimized to Y= 0.231%, C_b= 0.221%, and C_r= 0.149% and register usage and logical element usage were decreased to 36.59% and 67.57%, respectively.

並列關鍵字

Image Color Processor ； Color space conversion ； Pipeline architecture ； Folded architecture