內建特徵化一位元管線式類比數位轉換器的方法

A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC

周宇宏(Yu-Hung Chou)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.10021

摘要

本文提供一種對一位元管線式類比數位轉換器 ( Analog to Digital Converter ) 自我特徵化 ( self-characterization ) 的方法, 這個方法可以將轉換器每一級的電容不匹配比值和比較器的補償電壓這兩種主要的非理想參數數值化。
藉由加入本文所提出的測試電路把鄰近的兩級電路形成一個迴路, 接下來使用直流電壓作為輸入電壓並執行迴路測試 ( loop test ) , 然後記錄從開始測試到比較器狀態改變的時間長度, 最後透過該時間長度、自訂的輸入電壓和截止電壓推導出非理想參數。
本文使用數值模擬的方式去驗證該方法的正確性和精確度。

關鍵字

管線式類比數位轉換器 ； 內建自我特徵化

並列摘要

In this thesis, we present, for the 1-bit/stage pipelined Analog to Digital Converter, a self-characterization technique that quantifies the per-stage capacitor ratio and comparator offset—the two main nonlinearity sources. In the proposed loop test, two adjacent pipelined stages are reconfigured to form a loop. Then, DC test stimuli are applied. The capacitor ratio and comparator offset of the stage under test are derived from the recorded output sequences. Numerical simulations are performed to validate the proposed technique and its accuracy.

並列關鍵字

Pipelined ADC ； Built-In Characterization

參考文獻

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