具背景數位校正功能的分離式架構循環式類比數位轉換器的實現

Realization of a Cyclic ADC with Split Architecture and Digital Background Calibration

盧盈君(Ing-June Lu)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.10034

摘要

本文的目的為實做一具有背景數位校正功能的循環式類比數位轉換器，依循McNeil於2005年所發表分離式架構，建立整合類比數位轉換器與數位校正電路的實驗平台。所使用校正演算法，應用適應性濾波器原理，不需對前端類比電路注入額外校正訊號，對輸入訊號的影響最小。同時，分離式架構藉著數位校正的輔助，所佔面積只較傳統架構增加兩個比較器。
數位校正原理，假設相鄰的類比數位轉換器，其理想輸出可由兩者平均表示。將轉換器電路視為一特性未知的系統，即可設計一適應性濾波器，透過理想輸出與實際輸出的差值，利用最小均方法逼近此未知系統的特性參數，達到校正功能。
實驗晶片使用0.35微米互補式金氧半製程製作，操作電壓為3.3V，面積大小為1.5x1.5毫米平方。量測結果顯示，校正前分離式轉換器的解析度分別為45.70分貝與45.78分貝，相當於7.3有效位元與7.3有效位元；最大差分線性度分別為1.34最小位元與1.15最小位元，而最大積分線性度則為4.91最小位元與最小4.89位元（最小位元單位以十位元解析度計算）。數位電路在現場可程式邏輯閘陣列上實現，可操作之最高頻率為30.44百萬赫茲。整合後，系統的解析度由45.94分貝提升為54.43分貝，分別相當於7.33有效位元與8.74有效位元。校正前後的最大差分線性度分別為1.16最小位元與1.15最小位元，而最大積分線性度則由4.38最小位元改善至1.77最小位元。

關鍵字

分離式架構 ； 循環式類比數位轉換器 ； 背景數位校正 ； 適應性濾波器

並列摘要

This thesis realizes a cyclic analog-to-digital converter with background digital calibration according to the split-ADC architecture proposed by McNeill in 2005. The purpose is to establish an experimental platform on which the A/D converter and digital calibration circuit can be integrated. The calibration algorithm adopted does not require extra calibration signal to be injected in to the converter’s signal path, and therefore minimizes its effect on the input signal. Also, with the help of digital calibration, the overhead of implementing the split-ADC architecture is reduced. It only increases two extra comparators compared with the traditional architecture.
The underlying calibration principle assumes the average of two adjacent A/D converters as the ideal conversion result. The converter then may be taken as an unknown system whose characteristics can be probed with an adaptive filter. Using the assumed ideal conversion results and the real conversion output, one may apply the least-mean-square method. In this way, the actual parameters of the individual ADCs is found, completing the digital calibration procedure.
The chip has been fabricated using 0.35 um CMOS process, occupying area of 1.5x1.5 mm2. Measurement results show that the split-ADCs exhibit resolution of 45.70 dB and 45.78 dB, equivalent to ENOB of 7.3 bits and 7.3 bits, respectively. The maximum DNL of the converters are 1.34 LSB and 1.15 LSB, and the maximum INL are 4.91 LSB and 4.89 LSB, respectively. (LSB unit is calculated assuming 10-bit resolution) Digital calibration circuit is realized on FPGA, with maximum achievable operating frequency of 30.44 MHz. After integration, the system improves the resolution from 45.94 dB to 54.43 dB, which equivalently improves ENOB from 7.33 to 8.74. Maximum DNL are 1.16 LSB and 1.15 LSB before and after calibration, respectively, and maximum INL drops from 4.38 LSB to 1.77 LSB.

並列關鍵字

split architecture ； cyclic analog-to-digital converters ； background digital calibration ； adaptive filter

參考文獻

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