一個有時間偏移校正之多通道連續漸進式類比至數位轉換器

A Multi-Channel SAR ADC with timing mismatach calibration

張藝薰(Yi-Hsun Chang)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201601744

摘要

由於無線通訊系統的演進，對於高速取樣頻率以及中高解析度的類比數位轉換器的需求日漸增加。
本論文提出一個六位元每秒四十五億次取樣的時間交錯式之連續漸進暫存式的類比數位轉換器，以一個40奈米一般製程的CMOS製程實現。此架構由16個子通道之連續漸進暫存式的類比數位轉換器組成，以一個源極隨耦器作緩衝去推動4個通道類比數位轉換器為一組，共分成4組的方式，達到有效隔絕通道間的重疊以及高頻寬之效果。透過零交越（zero crossing）的偵測技巧，達成通道間的時間偏移補償。另一方面，在子通道之電容陣列作任意加權分佈（AWCA）可以去除比較器在轉換過程的動態偏移誤差。
實驗結果顯示在每秒四十億次的轉換下，DNL和INL分別為+0.17/-0.29 LSB和+0.20/-0.18 LSB。在每秒四十五億的轉換及輸入頻率為一億赫茲，SNDR以及SFDR分別為32.15 dB、41.04 dB。在1.2V的供應電壓下，功率消耗為 24.9 mW（不含I/O pad）。最後，品質因數（FoM）為159 fJ/c.-s.， 核心面積佔 0.195 平方毫米，全部面積大小為1.275平方毫米。

關鍵字

類比至數位轉換器 ； 時間交錯式 ； 連續漸進式 ； 高速 ； 低功率 ； 時間不匹配 ； 時間偏移校正

並列摘要

As the advance of wireless communication system, the requirements for ADC with high speed sampling rate and medium resolution gradually increase.
A 6-bit 4.5GS/s time-interleaved SAR ADC is presented in 40nm General process (GP) of CMOS technology in this thesis. The architecture consists of 16 SAR ADCs and is divided into 4 groups. Each group has 4 sub-ADC driven by a source follower as buffer to achieve isolation from overlapping channel and high bandwidth. In addition, the skew detection using zero crossing technique can compensate time skew error from channel mismatch without extra reference source. On the other hand, any-weighted-capacitor-array (AWCA)can suppress dynamic offset owing to the conversion process of comparator in sub-ADC.
The measurement results show that the linearity of DNL and INL are -0.17/-0.29 LSB and +0.2/-0.18 LSB, respectively at 4-GS/s with input frequency of 50 MHz. SNDR and SFDR are 32.15 dB and 41.04 dB respectively operated at 4.5GS/s with input frequency of 1 GHz. The power consumes 24.9 mW at 1.2V. Finally, the FoM is 159 fJ/c.-s. The active area occupies 0.195 mm2, and the overall chip occupies 1.275 mm2.

並列關鍵字

analog to digital converter ； time-interleaved ； SAR ； high speed ； low power ； timing mismatch ； time skew calibration

參考文獻

[1] Bob Verbrug et al., “A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS, ” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Paper, pp. 252–253, Feb. 2008.

[2] Bob Verbrug et al., “ A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 10, pp. 2080–2090, Dec. 2010.

[3] Zhiheng Cao, Shouli Yan, and Yunchu Li, “A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 0.13um CMOS,” Int. Solid-State Circuits Conf. Dig. Tech. Paper, pp. 542–543, Feb., 2008

[4] Chi-Hang Chan et al., "A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure," in IEEE Symp. VLSI Circuits Dig., Jun. 2012, pp. 86- 87.

[5] Hung-Yen Tai et al., “A 0.004mm2 Single-Channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS,” in IEEE Asian Solid-State Circuits Conf., 2013, pp. 277–280.