This thesis presents a successive-approximation ADC with dynamic element matching (DEM) technique. It can enhance the linearity of the reference DAC and thus reduce the area and power dissipation of the DAC. This prototype is fabricated in TSMC 40-nm LP 1P6M CMOS technology. It achieves an SNDR of 58.01 dB and an SFDR of 73.59 dB at 160MS/s. The maximum DNL is 0.66/-0.51 LSB and the maximum INL is 0.57/-0.61 LSB. The total active area occupies 0.012 mm2, and the ADC consumes 1.64 mW from a 1.1-V supply. The figure-of-merit (FOM) is 15.83 fJ/conversion-step.