一個十位元高速低功率之循序趨近式類比數位轉換器

A 10-bit High-Speed Low-Power Successive Approximation ADC

林文昱(Wen-Yu Lin)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.02221

摘要

本論文闡述一個十位元每秒八千萬次取樣之循序趨近式類比數位轉換器(Successive Approximation Analog-to-Digital Converter)，包含一個不固定基底之二元搜尋電容陣列，並以聯電 90-um CMOS 製程製作。使用此論文所提出電容陣列之類比數位轉換器達到更高的轉換速率以及更低的功率消耗，相較於以往的非二基底循序趨近式類比數位轉換器。並且使用時間交錯式架構 (Time-Interleaved) 更進一步的達到更高的轉換速率。
根據量測結果，本類比數位轉換器之 DNL 為 +0.9/-0.7 LSB，INL 為 +1.2/-1.3 LSB。在 80MS/s，輸入頻率為奈奎斯特頻率的情況下，SFDR 為 58.0dB，SNDR 為 49.3dB。在 1.2 伏特供應電壓下，消耗功率為 2.87mW。

關鍵字

十位元 ； 類比數位轉換器 ； 循序趨近式類比數位轉換器 ； 高速 ； 低功率

並列摘要

A 10b 80 MS/s CMOS Non-Binary SAR ADC using a non-constant radix binary search capacitor array is demonstrated in a standard 90-nm CMOS process. The ADC with the proposed capacitor array achieves higher conversion rate and lower power consumption compared to the prior non-binary SAR ADC works. Moreover, two-channel timeinterleaved method is utilized to achieve higher conversion rate.
The prototype circuit exhibits an DNL of +0.9/-0.7 LSB and a INL of +1.2/-1.3 LSB. The SNDR and SFDR achieves 49.3 dB and 58.0 dB at 80 MS/s for Nyquist input frequency. The ADC consumes 2.87 mW at 1.2V supply and occupies an active chip area of 0.14 mm2. The FoM is 155.5 fJ/conv.-step at 80 MS/s.

並列關鍵字

10-bit ； Analog-to-digital Converter ； Non-Binary SAR ADC ； High-Speed ； Low-Power

參考文獻

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