一個十位元高速的子範圍類比數位轉換器

本論文提出一個基於相位偵測的低雜訊比較器使用在子範圍類比數位轉換器。可以減低熱雜訊並且有較低機率發生亞穩態的特性。一個十位元的子範圍類比數位轉換器由3.9位元的快閃類比數位轉換器和7位元的循序漸近式類比數位轉換器組成。本論文提出的類比數位轉換器使用台積電的40奈米低功耗製程製做完成。此類比數位轉換器達到54.41dB訊號雜訊失真比，操作在160MHz的取樣頻率。在1.1V的電源供應下消耗2.7mW。品值因素達到39.4fJ/convertion-step。核心電路面積佔據0.0475平方毫米。

關鍵字

亞穩態；基於相位偵測的低雜訊比較器；子範圍類比數位轉換器

並列摘要

A low-noise phase-detector-based (PD-based) comparator is proposed for subrange analog-to-digital converters (ADCs) in this thesis. It can reduce the thermal-induced noise as well as the probability of the metastability. The 10-bit subrange ADC is composed of a 3.9-bit flash ADC and a 7-bit SAR ADC. The proposed ADC was fabricated in a 40-nm LP CMOS technology. The ADC achieves 54.41-dB SNDR at 160MS/s under a 1.1V supply voltage and consumes 2.7mW. The figure-of-merit (FOM) is 39.4 fJ/conversion-step. The active area is 0.0475 mm2.

並列關鍵字

Metastability ； Phase-detector -based comparator ； Subrange ADC

參考文獻

[1] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1μW Successive Approximation ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261-1265, July 2003.

[2] A. N. Karanicolas, H. S. Lee, and K. L. Bacrania, “A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207-1215, Dec. 1993.

[3] B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,“ IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.

[4] J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H. S. Lee, “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658-2668, Dec. 2006.

[5] L. Brooks and H. S. Lee, “A zero-crossing-based 8-bit 200 MS/s pipelined ADC,” IEEE J. Solid-State Circuits, vol. 42, no.12, pp. 2677-2687, Dec. 2007.

國際替代計量

一個十位元高速的子範圍類比數位轉換器

全文下載

主題瀏覽