利用時域量化器之可應用於無線感測網路的十位元混合型連續近似類比數位轉換器

A 10-bit Hybrid SAR ADC with Time-domain Quantizer for Wireless Sensor Network

陳彥君(Yan-Jiun Chen)

指導教授 ： 謝志成

國立清華大學/電機資訊學院/電機工程學系/碩士(2015年)

摘要

本研究論文提出一個十位元低電壓及高能源效率的混合型連續近似(SAR)類比數位轉換器(ADC)，可以應用於無線感測網絡的系統中。其操作在超低電壓的0.4伏特至0.7伏特，以維持良好的功率消耗表現，並可適用於不同頻段以配合各種應用需求。
所提出的混合型類比數位轉換器，在架構方面包含了粗調轉換器(Coarse ADC)以及細調轉換器(Fine ADC)，分別操作在電壓域以及時間域。粗調轉換器的部分使用7位元的VCM-based連續近似類比數位轉換器，此架構有較低的數位類比轉換器(DAC)切換功率消耗，並可以維持固定的共模準位電壓。轉換結束後的殘餘電壓在細調轉換部分會藉電壓控制延遲電路(VCDL)將電壓轉換至時間域，再利用Vernier 延遲架構的時間數位轉換器將其量化為3.5位元的編碼。其中額外的0.5位元為冗位元，可以藉此放寬粗調轉換器的需求並且容忍二個轉換器之間的偏移不匹配。此架構可以減少四倍的數位類比轉換器單位電容使用數量，以及放寬粗調轉換器的需求，使得比較器對於雜訊的需求降低，大幅減少其功率消耗。
此架構使用90奈米1P9M互補式金氧半導體製程製作，晶片總面積為1000×1000μm2，核心電路面積為120×340μm2，在0.4至0.7伏電源電壓及相對應的250千至4百萬取樣頻率操作時，以及在Nyquist輸入訊號頻率下，此晶片實現SNDR從53.7至54.8dB，其對應的ENOB為8.63至8.81，功率消耗為0.2至8.3微瓦，等效的figure of merit (FoM)為2.02至5.16fJ/conversion-step。

關鍵字

類比數位轉換器 ； 低功耗

並列摘要

This thesis presents an ultra-low voltage and power efficient 10-bit hybrid
successive-approximation register (SAR) analog-to-digital converter (ADC) for wireless sensor
network.
The proposed ADC operates at ultra-low supply voltage from 0.4V to 0.7V to save power
consumption. The hybrid architecture is proposed to reduce the total amount of capacitance and
relieve requirement of comparator, and the ADC is composed of coarse and fine conversions by 7-bit
SAR ADC and 3.5-bit time-domain quantizer, respectively. Using residue voltages generated by
coarse ADC and converting it to time-domain, the fine ADC detects the least three bits with 0.5-bit
redundancy by Vernier delay structure.
The prototype was fabricated using 90nm 1P9M CMOS technology and core area is only
120×340μm2. At 0.4-to-0.7V supply and 250KS/s-to-4MS/s sampling rate, the ADC achieves SNDR
from 53.7 to 54.8dB corresponding ENOB from 8.63 to 8.81 at Nyquist-rate input and consumes
0.2-to-9.3 W power consumption, resulting in a figure of merit (FOM) from 2.02-to 5.16 fJ
/conversion-step.

並列關鍵字

Analog to Digital Converter ； Low Power ； Time domain ； SAR ADC

參考文獻

[1] P. Harpe, et al., "A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step," IEEE J. Solid-State Circuits, vol.48, no.12, pp. 3011-3018, Dec. 2013.

[2] M. Ahmadi, et al., "A 3.3fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocation," IEEE CICC , pp. 22-25 Sept. 2013.

[3] P. Harpe, et al., "An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR," IEEE ISSCC Dig. Tech. Papers, pp. 194-195, Feb. 2014.

[4] V. Giannini, et al., "An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 238-239,610, Feb. 2008.

[5] P. Harpe, et al., "A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/ conversion-step," IEEE ISSCC Dig. Tech. Papers, pp. 472-474, Feb. 2012.