一個十位元每秒一億次取樣使用保留與反轉切換之多位元逐漸趨近式類比數位轉換器

A 10Bit 100MS/s With Stay&Inverse switching Multi-Bit Successive Approximation ADC

葉人豪(Ren-Hao Ye)

指導教授 ： 蔡 宗 亨

國立中正大學/工學院/電機工程學系/碩士(2014年)

摘要

本論文實現了一個十位元每秒一億次取樣使用保留與反轉之多位元逐漸逼近式類比數位轉換器，解析度10位元，取樣速度為100MS/s，功率消耗0.879mW，FOM為10.94(fj/Conv.-step)，使用的是TSMC GUTM90nm CMOS製程。因使用多位元逐漸逼近式類比數位轉換器，以及所提出的保留與反轉切換方式，有效減少輸入電容陣列大小，較傳統逐漸逼近式類比數位轉換器減少75%。除此之外，使用所提出的切換方式在功率消耗，也較傳統逐漸逼近式類比數位轉換器減少97.92%。在本論文中，為了增加比較器在最小位元判斷週期的判斷速度，因此使用LSB校正機制，除此之外，此方法還可減少產生參考電壓電路所需要的電容陣列大小，較傳統減少75%。

關鍵字

類比數位轉換器 ； 逐漸趨近式類比數位轉換器 ； 多位元

並列摘要

A 10Bit 100MS/s with Stay&Inverse multi-bit successive approximation analog-to-digital converter(SA ADC) is proposed and implemented.The converter is implemented by TSMC 90nm CMOS process technology. At 100MS/s, the ADC achieves an SNDR of 59.833dB and consumes 0.879mW,resulting in a figure of merit(FOM) of 10.94 fJ/conversion-step.By using the Stay&Inverse switching,the input capacitance is reduced about 75%, compared to the conventional SA ADC.Furthermore,the average switching energy is reduced about 97.92%.In this paper,in order to increase the determination rate of comparator at LSB determine step. The other, using the LSB correction , the generating a reference voltage circuit can reduce the capacitor array , that reduced about 75%.

並列關鍵字

Multi-bit ； ADC ； SAR ADC

參考文獻

[1] S. J. Chang, et al., “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,”IEEE Journal of Solid-State Circuists, vol. 45,no. 4,pp. 731-740,April 2010.

[2] V. Hariprasath,J. Guerber,S.-H Lee,and U.-K Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” ELECTRONICS LETTERS,vol. 46,no. 9,pp. 620-621,April 2010.

[3] Y. K. Chang, C. S. Wang, and C. K. Wang, “A 8-bit 500 KS/s low power SAR ADC for bio-medical application,” IEEE Asian Solid-State Circuits Conference, Nov. 2007,pp. 228-231.

[4] B. P. Ginsburg and A. P. Chandrakasan, “A 500 MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array ADC, ”IEEE Journal of Solid-State Circuits,vol. 42,no 4,pp. 739-747,April 2007.

[7] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, Oxford, 2002.