一個十位元每秒兩千萬次取樣帶冗餘位逐漸趨近式類比數位轉換器

A 20MS/s 10-bit Successive-Approximation Analog to Digital Converter with Redundancy

徐志豪(CHIH-HAO HSU)

指導教授 ： 陳淳杰

中原大學/電機資訊學院/電子工程學系/碩士(2022年)

https://doi.org/10.6840/cycu202201230

摘要

如今電子產品除了要效能好，亦追求低功耗與輕薄短小，由於半導體製程技術的進步，帶動了積體電路設計的成長，許多低功耗的晶片得以實現，在眾多類比數位轉換器中，逐漸趨近式(Successive-Approximation)由於大部分元件皆由數位邏輯電路所構成，且整個電路僅需一組比較器即可，大幅地降低了資料轉換所需的功耗。
本論文完整製作一個10-bit 20MS/s SAR ADC，架構採用分段式電容陣列數位類比轉換器，使用TSMC 0.18um 1P6M CMOS製程，電源供應1.8V，輸入頻率為1.97265625MHz進行模擬，訊號雜訊與失真比(SNDR) 60.71 dB，有效位元數(ENOB) 9.79-bit，功耗0.92 mW，品質因數(FOM) 52f J/conversion-step，核心晶片佈局面積0.31*0.21〖mm〗^2，晶片總佈局面積1.163*1.169〖mm〗^2。
最後設計規格同樣為10-bit 20MS/s SAR ADC，架構改成帶冗餘位演算法，將MSB電容拆解並分配至原電容陣列中，達到電容切換速度的提升，並在栓鎖電路前加上一級前置放大器，用以降低誤差，提高比較器的精準度。使用相同製程與輸入頻率進行模擬，訊號雜訊與失真比(SNDR) 61.93 dB，有效位元數(ENOB) 9.99-bit，功耗3.024mW，品質因數(FOM) 148.7f J/conversion-step。
關鍵字：逐漸趨近式類比數位轉換器；分段式電容陣列；帶冗餘位演算法

關鍵字

逐漸趨近式類比數位轉換器 ； 分段式電容陣列 ； 帶冗餘位演算法

並列摘要

Nowadays, in addition to high performance, electronic products also pursue low power consumption, lightness, and compactness. Due to the advancement of semiconductor process technology, the development of integrated circuit design has led to the realization of many low-power chips. Among many analog-to-digital converters, Successive-Approximation type greatly reduces the power consumption required for data conversion because most of the components are composed of digital logic circuits, and the entire circuit only needs one set of comparators.
In this thesis, a complete 10-bit 20MS/s SAR ADC is fabricated. The architecture uses a segmented capacitor array digital-to-analog converter. The TSMC 0.18um 1P6M CMOS process is used. The power supply is 1.8V, and the input frequency is 1.97265625MHz. SNDR 60.71 dB, effective number of bits (ENOB) 9.79-bit, power consumption 0.92 mW, figure of merit (FOM) 52f J/conversion-step, core chip area 0.31*0.21〖mm〗^2, the total area of the chip is 1.163*1.169〖mm〗^2.
The final specification is also a 10-bit 20MS/s SAR ADC. The architecture is changed to a redundancy algorithm. The MSB capacitors are disassembled and allocated to the original capacitor array to improve the capacitor switching speed. A preamplifier is added to reduce the error and improve the accuracy of the comparator. Using the same process and input frequency for simulation, the signal-to-noise-to-distortion ratio (SNDR) is 61.93 dB, the effective number of bits (ENOB) is 9.99-bit, the power consumption is 3.024mW, and the figure of merit (FOM) is 148.7f J/conversion-step.
Keywords: SAR ADC；Segmented capacitor array；Redundancy algorithm.

並列關鍵字

SAR ADC ； Segmented capacitor array ； Redundancy algorithm

參考文獻

[1] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, and Ying-Zu Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010.

[2] 戴正洋，(2020.07)， 採用分段式電容陣列的12位元25MS/s 逐漸趨近式類比數位轉換器，中原大學電子工程研究所碩士班論文

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[5] 沈佳穎，(2021.07)，一個十位元每秒兩千萬取樣頻率混合溫度計碼逐漸趨近式類比數位轉換器，中原大學電子工程系研究所碩士班論文