一個十位元每秒兩千萬取樣頻率之二階逐漸趨近式類比數位轉換器

A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter

黃奕瑋(Yi-Wei Huang)

指導教授 ： 陳淳杰

中原大學/電機資訊學院/電子工程研究所/碩士(2015年)

https://doi.org/10.6840/CYCU.2015.00512

摘要

本論文之研究目的在於提出一個二階式逐漸趨近類比數位轉換器架構，來降低逐漸趨近式類比數位轉換器的總取樣電容值(為逐漸趨近式類比數位轉換器佈局面積增加之主要因素)以及降低其中數位類比轉換器子電路之電容充電時間並且降低逐漸趨近式類比數位轉換器之開關切換所消耗的功率，除此之外，本論文也將分析寄生電容所帶來的影響以及二階式逐漸趨近類比數位轉換器的設計方式。
本篇論文設計一個使用單調式電容開關機制的十位元每秒兩千萬取樣頻率之二階式逐漸趨近類比數位轉換器。設計平台使用TSMC 0.18μm 1P6M CMOS製程，在電源供應1.8V的情況下，功率消耗23.4mW，訊號雜訊與失真比SNDR為56.11dB，有效位元數ENOB為9.03bits，品質因數(FOM)為2.238 pJ/conversion-step。晶片佈局面積為1.175mm×1.175mm，核心電路面積為0.360mm×0.375mm。

關鍵字

逐漸趨近式暫存器 ； 類比數位轉換器 ； 單調式電容開關機制 ； 二階式

並列摘要

This paper proposes a Two-Step Successive-Approximation Analog to Digital Converter structure technique to reduce the total capacitance of the DAC capacitor network (The dominant source of the layout area of SAR ADCs), the settling time of the ADC circuit and the switching energy of the capacitor network. In addition, this project also analyzes the parasitic capacitance of the circuit and summarizes an optimization design procedure of Two Step Successive-Approximation Analog-to-Digital Converters.
In this work, a 10-bit 20MS/s two-step successive approximation register analog to digital converter is proposed by using monotonic capacitor switching procedure. Design platform is TSMC 0.18μm 1P6M CMOS process. The power consumption of this work is 23.4mW at 1.8V power supply. This converter achieves SNDR 56.11dB, 9.03 Effective Number of Bits(ENOB). The Figure of Merit(FOM) is 2.238 pJ/conversion-step. The chip area is 1.175mm×1.175mm, and the core area is 0.360mm×0.375mm.

並列關鍵字

Successive Approximation Register ； Analog-to-Digital Converter ； Monotonic Capacitor Switching Procedure ； Two-Step

參考文獻

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