應用於一個十位元每秒兩千萬取樣頻率之二階逐漸趨近式類比數位轉換器之放大器改良

An Improved Amplifier Applied to A 10-bit 20MS/s Two-Step SAR Analog toDigital Converter

周思凱(Si-Kai Zhou)

指導教授 ： 陳淳杰

中原大學/電機資訊學院/電子工程研究所/碩士(2017年)

https://doi.org/10.6840/cycu201700456

摘要

本論文目的為改良應用於二階式逐漸趨近類比數位轉換器餘值放大器架構，以此降低放大器本身所需的功耗進而降低二階逐漸趨近式類比數位轉換器的整體功耗值。使用分區電路方式再分別調整各區塊所佔的電流比例以及採用Class-AB觀念設計輸出級的MOS元件的Q點(為放大器增加功耗的主要原因，也是目前整個SAR ADC功耗最大的部分)，有效提升整體放大器電路對電源使用的效率。除此之外，本文將分析寄生電容對整體電路所帶來的影響以及介紹二階式逐漸趨近類比數位轉換器的設計方式。
本文改良一個採用折疊式疊接架構結合非反向放大器架構應用於十位元每秒兩千萬取樣頻率之二階式逐漸趨近類比數位轉換器的放大器，設計平台使用TSMC 0.18μm 1P6M CMOS製程，在電源供應為1.8V之情況時，增益為74.56dB，f3dB為0.36MHz，放大器功率消耗0.9342mW，面積為84.89µm×33.83µm。

關鍵字

非反相放大器；軌對軌；電流比較器；逐漸趨近式暫存器；類比數位轉換器；單調式電容開關機制；二皆式

並列摘要

This paper purpose an improvedamplifier applied to Two-Step Successive-Approximation Analog-to-Digital Converter structure technique to reduce the power of the amplifiereven the total power of the Two-Step Successive-Approximation Analog-to-Digital Converter. The use of partition circuit and then adjust the current proportion of each block and the use of Class-AB concept design output of the MOS component Q point (The dominant powerconsumption of the amplifier, also the most of power consumption of the SAR ADC), effectively improve the efficiency of the amplifierfor power supply. In addition, this paper will analyze the impact of parasitic capacitance of the circuit and summarizes an optimization design procedure of Two Step Successive-Approximation Analog-to-Digital Converters.
In this work, improve an amplifier applied to a 10-bit 20MS/s two-step successive approximation register analog to digital converter is proposed by usingthe structure of folded cascade and non-inverting amplifier. Design platform is TSMC 0.18μm 1P6M CMOS process. The gain of this work is 74.56dB, f3dB of this work is 0.36MHz, power consumption of this work is 0.9342mW at 1.8V power supply. The chip area is 84.89µm×33.83µm。

並列關鍵字

Non-inverting amplifier；Rail-to-rail；Current comparator；Successive Approximation Register；Analog-to-Digital Converter ； Monotonic Capacitor Switching Procedure；Two-Step

參考文獻

[11]黃奕瑋，(2015.7)，一個十位元每秒兩千萬取樣頻率之二階逐漸趨近式類比數位轉換器，中原大學電子工程系研究所碩士班論文。

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