應用放大器共享技巧之可重置式十位元兩億赫茲管線式類比數位轉換器

A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter with Opamp-Sharing Technique

何家齊(Chia-Chi Ho)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.03359

摘要

近年來，隨著無線通訊應用的快速成長，不同的無線通訊規格也相繼出現，便需要不同的收發機，因此，如何整合這些通訊系統在同一收發機內成為一個熱門的議題。軟體無線電(Software-Defined Radio，SDR)技術[1]即是指在目前各種不同的無線通訊規格中，藉由在不同信號調變方式之間建立互通性，共用相同類比射頻的前端電路，最後再由軟體進行信號解調以及處理。如此就能使用單一收發機，同時進行多規格之通訊。然而，欲完成此種軟體無線電收發機，便不可或缺一個具有不同解析度及轉換頻率的多規格類比數位轉換器。

管線式類比數位轉換器已被廣泛使用於中解析度且高速的應用中。本論文中提出改良電容切換運算及可調整運算放大器，使管線式類比數位轉換器在不同規格的需求下達到更有效率的功率耗損。所設計的類比數位轉換器，其數位碼輸出的訊雜比可達48.6 dB。本管線式類比數位轉換器採用九十奈米CMOS製程製作，其中核心面積為0.27平方毫米。利用運算放大器與電容共享的技巧，在一伏供應電壓、兩億赫茲轉換速率下，可將核心消耗的功率降低至32毫瓦，再加上運算放大器的調變，於一億赫茲與五千萬赫茲的轉換速率下可分別將功率再降至18.5及13毫瓦。最後，在本論文末，針對管線式架構與近來快速發展的連續漸進式類比數位轉換器進行分析，以引導未來的發展方向。

關鍵字

無線通訊 ； 可適性系統 ； 軟體無線電 ； 類比數位轉換 ； 運算放大器共享技巧 ； 管線式類比數位轉換器 ； 連續漸進式類比數位轉換器

並列摘要

In recent years, applications of wireless communication have been growing rapidly. Meanwhile, more specifications of wireless communication have been developed, so different receivers are needed. Therefore, it is desirable to combine these systems into one receiver. Software-Defined Radio, SDR [1], is one of these techniques to realize a multi-standard receiver by processing signal in the software. By this method, resources such as analog RF frontends and analog-to-digital converters (ADCs) can be shared between different modulations. To do so, an ADC that is able to adjust its resolution and conversion rate is necessary.

The pipelined ADC has been widely utilized in mid-resolution, high-speed applications. In this thesis, a switched-capacitor technique and a power reconfigurable opamp are proposed, which allow the system to optimize its power consumption with system bandwidth and resolution. Output codes of the designed ADC exhibit a SNDR of 48.6 dB. Fabricated in the 90nm CMOS technology, the core of the reconfigurable pipelined ADC occupies 0.27mm2. The opamp-sharing and capacitor-sharing techniques reduce the core power consumption to 32mW from a 1V supply voltage at 200MS/s. By the reconfiguration, the power consumption can be reduced to 18.5mW and 13mW at the conversion rate of 100MS/s and 50MS/s, respectively. At the end of this thesis, an analysis is performed to compare pipelined architectures with fast-growing SAR ADCs. This analysis helps the direction of future development.

並列關鍵字

Wireless communication ； Software-Defined Radio ； analog-to-digital conversion ； opamp-sharing technique ； pipelined ADC ； SAR ADC

參考文獻

[1] A. A. Abidi, “The Path to the Software-Defined Radio Receiver,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 954-966, May, 2007.

[2] H. van der Ploeg and B. Nauta, Calibration Techniques in Nyquist A/D Converters, Springer, Dordrecht, 2006.

[3] B. Murmann and B. E. Boser, “A 12-bit 75MS/s Pipelined ADC Using Open-Loop Residue Amplification,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.

[4] B. Ginetti, P. G. A. Jespers, and A. Vandemeulebroecke, “A CMOS 13-b Cyclic RSD A/D Converter,” IEEE J. of Solid-State Circuits, vol. 27, pp. 957-965, Jul. 1992.

[7] S. H. Lewis, "Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications," IEEE Trans. Circuits Syst II, vol. 39, pp. 515–523, Aug. 1992.