十位元源極驅動器暨操作於2GS/s快閃式類比數位轉換器

本論文中提出了兩個電路，一個是十位元給液晶顯示器使用之源極驅動電路，另一個是應用於取樣頻率二十億次快閃式類比數位轉換電路。第一個電路為十位元液晶顯示器源極驅動電路，利用二階式的方法，設計把十位元的DAC設計成六位元加四位元，可以有效達到減少面積，文中並針對二階式數位類比轉換器會遇到的負載問題提出新架構解決，且針對源極驅動器設計出一個新的輸出緩衝放大器電路，模擬結果顯示INL範圍0.08LSB~-0.3LSB；DNL範圍為0.028LSB~-0.035LSB，晶片面積一個通道為0.0215mm2。第二個電路為應用於取樣頻率二十億次快閃式類比數位轉換器，文中針對追蹤取樣電路，前置放大器，比較器詳細分析說明。並且為了消除製程變異造成的誤差，我們採用電阻平均技術作誤差的校正，模擬結果顯示，類比數位轉換器在輸入頻率達996MHz時ENOB為5.8bit，佈局面積為1.9mm2。

關鍵字

液晶顯示器；源極驅動器；緩衝器；快閃式類比數位轉換器；取樣電路；平均電阻；前置放大器；比較器

並列摘要

In this thesis, two circuits are proposed. The first one is a 10-bit source driver for the TFT-LCD panel, and the second one is a 2GHz samples/s 6-bit Flash ADC. In the first circuit, the two-stage resistive divider DAC is adopted for the 10-bit source driver. The 10-bit decoder is divided into 6-bit and 4-bit to effectively reduce chip area. The new technique, a current-injection DAC, is proposed to overcome the loading problems of the two-stage architecture. Besides, a new output buffer for the source driver is introduced to save more power. The simulation result of the INL range is 0.07LSB~-0.3LSB, and the DNL range is 0.3LSB~-0.03LSB. The chip area is 0.0215mm2 per channel. In the second part of this thesis, A 6-bit Flash ADC with 2GHz samples/s is presented. The design considerations and analyses for the block circuits of ADC, like the track and hold circuit, the preamplifier, and the comparator are also explained in detail. To alleviate the random offset caused by the process variation, the resistive averaging technique is adopted. The simulation result for the ENOB of this ADC is 5.8-bit when the input frequency is 996MHz. The chip area is 1.9mm2.