適用於電力線通訊系統之十位元高速管線式類比數位轉換器

Design of 10 bits High Speed Pipelined ADC for Power-Line Communication System

宋東鴻(Tung-Hung Sung)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.02332

摘要

由於高速低功率的特性，管線式類比數位轉換器目前被廣泛地運用在中高解析度的現代通訊系統裡。在本論文中我們藉由台積電90奈米的製程實現了兩個高速的十位元管線式類比數位轉換器。兩顆晶片分別使用了1.5位元和2.5位元的架構來實現；並且運用了放大器分享以及動態輸入範圍加倍的技術降低了功率消耗。其中1.5位元架構的類比數位轉換器另外被整合在我們電力線通訊系統的類比前端電路的晶片當中。
在200MS/s的取樣頻率下，對於1MHz的輸入頻率第一顆類比數位轉換器晶片的SNDR、SFDR和ENOB分別是43.52 dB、55.01 dB以及6.94位元；在180MS/s的取樣頻率下，對於1MHz的輸入頻率第二顆類比數位轉換器晶片的SNDR、SFDR和ENOB分別是35.06 dB、45.34 dB以及5.53位元。另外功率消耗跟FoM的部分，第一顆晶片的功率消耗為51.2毫瓦，FoM為2.08 pJ/convstep；第二顆晶片的功率消耗為37.2毫瓦；FoM為4.47 pJ/convstep。

關鍵字

電力線通訊系統 ； 管線式類比數位轉換器 ； 1.5位元架構 ； 放大器分享 ； 動態範圍加倍

並列摘要

Pipelined ADC is widely used in modern communication system owing to the fact that it has the characteristic of low power, mid-high resolution and high speed. In this thesis, we propose two different architectures of 10 bits 200MS/s pipelined ADC. In the first ADC, 1.5-bit architecture is used. To reduce the power consumption, two techniques, OP-amp sharing and dynamic range doubling (DRD) are applied in this ADC. Moreover, this ADC is also applied in another chip: the analog front-end of the power-line communication system. In the second ADC, 2.5-bit architecture is used and we merge the sample and hold circuit and the 1st MDAC circuit into one stage by using OP-amp sharing. Besides, DRD technique is also applied in this ADC. Both these two chips are fabricated in TSMC 90nm process.
As for measurement results, with the 1MHz input frequency and the 200MS/s sampling rate, the SNDR, SFDR and ENOB of the first ADC are 43.52 dB, 55.01 and 6.94 bits respectively. Besides, with the 1MHz input frequency and the 180MS/s sampling rate, the SNDR, SFDR and ENOB of the second ADC are 35.06 dB, 45.34 dB and 5.53 bits respectively. In addition, the power consumption and the FoM of the first ADC are 51.2mW and 2.08 pJ/convstep; the power consumption and the FoM of the second ADC are 37.2mW and 4.47 pJ/convstep.

並列關鍵字

power-line communication ； pipelined ADC ； 1.5-bit per stage ； OP-amp sharing ； dynamic range doubling

參考文獻

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