應用在電力線通訊系統之高速低功率管線式類比數位轉換器

A High Speed and Low Power Pipelined ADC for Powerline Communication System

林慶峰(Ching-Fong Lin)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.02622

摘要

管線式類比數位轉換器已被廣泛地使用在中高解析度且高速的通訊系統中。在本論文中我們實現了兩個高速且低功率的十位元管線式類比數位轉換器，其操作頻率分別為100MS/s以及200MS/s。其中高速的版本被整合在本實驗室電力線通訊系統中的類比前端接收發器，與可變增益放大器結合作為系統上的接收器。
本次設計的兩個晶片皆由台積電的90nm製程製作，利用1.5 bit的架構達到高速操作的應用。運算放大器共享技巧也被用來減少放大器的數目，藉此降低消耗功率。另一方面，使用動態輸入範圍加倍的技巧，降低訊號在管線式類比數位轉換器裡操作的擺幅大小。此技巧不只提高訊號等效的輸入動態範圍，也有效地降低運算放大器增益及頻寬的規格，對節省功率也有所幫助。從佈局後模擬可以看出，操作頻率由100MS/s提升到200MS/s時，其FoM由126fJ/step降到100fJ/step。根據量測的結果，本晶片在50MS/s的取樣頻率下，對於5MHz的輸入頻率下SNDR為42.5dB，SFDR為47.2dB。當時脈升至100MS/s時，SNDR及SFDR分別降為31.9dB及45dB。在100MS/s的操作頻率之下，電路的消耗功率為11mW。

關鍵字

高速 ； 低功率 ； 管線式 ； 導管式 ； 類比數位轉換器

並列摘要

Pipelined analog-to-digital converters (ADCs) have been widely utilized in high speed communication system for mid-high-resolution and high-speed sampling rate. In this thesis, we have implemented two high speed and low power 10-bit pipelined ADCs with sampling clock 100MS/s and 200MS/s respectively. The 200MS/s ADC is used as an analog front-end transceiver of HomePlug AV 2 power line communication system, which is combined with programmable gain amplifier as the receiver of whole system.
Implemented in TSMC 90nm technology, both chips applied 1.5-bit architecture to achieve high speed application and op-amp sharing technique to reduce the amount of op-amps being used to reduce power dissipation. Moreover, we use dynamic-range-doubling (DRD) technique to enlarge the dynamic range in pipelined ADC. The DRD technique not only increases the effective input range, but also decreases the gain and bandwidth requirement of op-amps. In post-layout simulation results of these two designs, FoM is 130fJ/step increased to 110fJ/step when the sampling frequency is raised from 100MS/s to 200MS/s, respectively. According to the measuring results, with 5MHz input frequency, the SNDR and SFDR achieve 42.5 dB and 47.5 dB at 50MS/s. The SNDR and SFDR are reduced to 31.9 dB and 45 dB at 100MS/s with 10MHz input frequency. The power consumption is 11mW at 100MS/s conversion rate.

並列關鍵字

high speed ； low power ； pipelined ADC ； ADC

參考文獻

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[8] T. Cho and P. R. Gray, "A 10-b 20Msample/s 35mW pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.