以全差動第二代電流傳輸器為基礎之新型管線式類比數位轉換器

Design of New Fully Balanced Second-Generation Current Conveyor Based Pipelined A/D Converter

巫興彥(Hsing-Yen Wu)

指導教授 ： 黃育賢

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2006年)

摘要

在所有的架構中，快閃式類比數位轉換器 (Flash A/D Converter) 是目前最快的一種架構，然而在提高解析度時，整體面積與消耗功率卻呈現大幅度的增加。因此，管線式類比數位轉換器 (Pipelined A/D Converter) 相較於快閃式類比數位轉換器更適合發展快速與高解析度的架構。管線式類比數位轉換器的效能往往取決於所使用的運算放大器，所以運算放大器的設計常常為管線式類比數位轉換器的設計重點。有別於一般採用運算放大器為核心電路的設計方式，管線式類比數位轉換器的兩個主要電路：前端取樣保持電路(Sample/Hold Circuit)以及相乘式數位類比轉換器(Multiplying DAC)，採用以第二代電流傳輸器(Second-Generation Current Conveyor，CCII)為架構的電路已經被設計出來了。而在訊號傳輸的架構中，採用全差動(Fully Differential)的架構有高雜訊免疫(Noise Rejection)以及兩倍的訊號擺幅(Signal Swing)等優點，因此被廣泛採用於類比數位轉換器中。因此，在此論文中，採用了全差動式電流傳輸器(Fully-Balanced CCII，FBCCII )來設計管線式類比數位轉換器，其中在MDAC的部份，提出了新的電路，來抵抗電荷注入(Charge Injection)的效應。整體電路採用台灣積體電路公司（TSMC）0.18um 1P6M製程來實現，解析度為7位元，取樣頻率為12.5MHz，INLMAX為1.3LSB，DNLMAX為0.7LSB，晶片面積為1.5×1.4mm2。

關鍵字

類比數位轉換器 ； 管線式 ； 電流傳輸器 ； 相乘式數位類比轉換器

並列摘要

Among all the ADC architectures, the flash ADC is the fastest one. However, chip area and power consumption grow exponentially as the resolution increases. The pipelined architecture is more suitable for high speed and high resolution applications than the flash architecture. The accuracy of the pipelined ADC greatly depends on OP Amp’s performance. As the result, OP Amp is the most critical circuit when engineers design a pipelined ADC. Unlike the conventional design of pipelined ADC, the sample-and-hold(S/H) circuit and multiplying DAC(MDAC) based on the second-generation current conveyor have been developed instead of the OP Amp. Fully differential architecture is commonly adopted to develop signal process system because of its merits, such as highly noise rejection and double signal swing. Thus, a fully-balanced second -generation current conveyor is adopted to design the pipelined ADC. Besides, a new MDAC is designed to eliminate the effect of charge injection. The pipelined ADC is designed and implemented with TSMC 0.18um 1P6M process. The resolution of the ADC is 7 bits, sampling rate is 12.5Mhz, INLMAX is 1.3LSB, and DNLMAX is 0.7LSB, and chip area is 1.5×1.4mm2.

並列關鍵字

A/D converter ； Flash ； Pipelined ； Current conveyor,MDAC

參考文獻

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