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  • 學位論文

應用於數位音頻系統之微功率開關電容三階三角積分調變器設計

Design of Micropower Switched-Capacitor Third-Order Sigma-Delta Modulator for Digital Audio Applications

指導教授 : 黃育賢 陳建中

摘要


隨著現今行動電子產品的發展及需求日漸成長,主要著重設計輕薄、電池能維持較長的工作時間,以及提供高的品質,如手機、MP3等可攜式的產品。在可攜式的產品中,電池的重量及大小常是造成產品重量以及大小的關鍵,因此減低功率消耗可以有效減少電池的個數以及電池的壽命。而這類的產品上,軟體與硬體大多都是以數位方式去實現,因此需要一個高解析度、低功率消耗且面積小的類比數位轉換器。為達到上述特點,三角積分調變器扮演了一個很重要角色。 本論文設計一個低電壓/微功率三階三角積分調變器,可應用於數位音頻系統上。為了可攜性的考量,因此本調變器使用單端電源為1.5V,可有效降低電池重量,適合用於有輕便性需求的產品上,且本調變器總耗電量僅788μW,能有效的增加電池使用壽命。由於低電壓系統設計,使得CMOS傳輸閘開關無法正常的導通或關閉,因此,一般低電壓的電路設計亦會在此介紹。在調變器電路的實現上,我們採用全差動式開關電容電路,並以TSMC 0.35μm Mixed-Signal 2P4M製程參數進行模擬,整體佈局面積為1.128 x 1.128 mm2(含I/O PAD)。在超取樣率為64,信號頻寬為20kHz時,所得到的最大信號與雜訊失真比為81.4dB,有效解析度為13.23 bits,動態範圍為80.2dB。

並列摘要


In response to the increasing demands for greater mobility and more powerful functions, design of portable electronic devices are moving toward smaller size, slimmer body, lighter weight, longer battery life, and greater efficiency, such as cellular phones, mp3 players…etc. The weight and size of a portable device, however, is determined to a great extent by the batteries it uses. Therefore, to achieve smaller size and lighter weight, the number of batteries should be reduced, and this can be done by decreasing the chip’s power consumption. Since most of today’s portable devices rely on digital circuits in terms of both software and hardware, an analog-to-digital converter (ADC) is needed. The thesis accordingly designs a sigma-delta modulator (SDM) capable of obtaining high resolution to serve as an improved ADC. This thesis presents a low-voltage micropower 3rd-order sigma-delta modulator for digital audio applications. For reducing the weight of battery to facilitate the design of smaller and lighter portable products, the proposed modulator uses only a single-end power supply of 1.5V. Moreover, the modulator reports a power consumption as low as 788μW, making it more capable of extending battery life. As a low voltage system is used, the switch driving problem in circuit design is also discussed. The modulator is implemented with a fully-differential switched capacitor (SC) circuit and simulated with the parameters of the TSMC 0.35μm CMOS 2P4M process. With a chip area of 1.128 x 1.128 mm2, the post-simulation results show the modulator capable of achieving a peak SNDR of 81.4dB and a dynamic range of 80.2dB at an oversampling ratio of 64 within a signal bandwidth of 20kHz. The resolution produced reaches 13.23 bits.

參考文獻


[10] 張銘傑, 以電流傳輸器為基礎之三角積分調變器設計, 碩士論文, 國立臺北科技大學電腦與通訊研究所, 2005.
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