以電流傳輸器為基礎之三角積分調變器設計

Design of the Sigma-Delta Modulator Based on Current Conveyors

張銘傑(Ming-Chieh Chang)

指導教授 ： 黃育賢

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2005年)

https://doi.org/10.6841/NTUT.2005.00150

摘要

類比數位轉換器已發展數十年，以速度考量，則以快閃式類比數位轉換器為主﹔在解析度考量上，則以三角積分類比數位轉換器為主，其解析度可以從12~24 位元。三角積分調變器為三角積分類比數位轉換器之前端，其應用了超取樣定理和雜訊移頻，所以能使解析度大大的提高。然而一個三角積分調變器的好壞往往取決於積分器、增益係數、回授係數等的設計。
本篇論文主要是在討論使用第二代電流傳輸器去實現一個積分器，之後利用其特性，去實現整個三角積分調變器，使用此一方式有別於以往以運算放大器為整體架構核心的設計方式。整個晶片以台灣積體電路製造公司 TSMC 0.35 2P4M CMOS製程來實現，根據模擬結果，其解析度在二階三角積分調變器可以達到43dB，動態範圍為50dB，功率消耗為53mW。

關鍵字

類比數位轉換器 ； 第二代電流傳輸器 ； 積分器 ； 三角積分調變器

並列摘要

The A/D Converter (ADC) has already been developed in decades. When we considered the speed, it rely mainly on flash ADC﹔and considered the resolution, it rely mainly on sigma-delta ADC with 12~24 bit resolution. The Sigma-Delta modulator(SDM) is the front-end of the Sigma-Delta ADC and it uses the oversampling and noise shaping which can improve the resolution. The properties of the SDM are decided by several factors, such as integrator, gain coefficient , feedback coefficient, etc.
Unlike other designs, the thesis presents the integrator which based on second-generation current conveyor (CCII) as the core to design the SDM. This Chip is designed and implemented with TSMC 0.35um 2P4M CMOS process. With the simulation results, the SNR of the second-order SDM is 43dB and the dynamic range is 50dB. The power consumption is 53mW.

並列關鍵字

A/D Converter ； Integrator ； Second-Generation Current Conveyor ； Sigma-Delta Modulator

參考文獻

[1] A.M.Ismail, A.M.Soliman, "Wideband CMOS current

2369, DEC 1998.

[2] A.Awad, A.M.Soliman, "New CMOS realization of the CCII-

," IEEE Transactions on Circuits and Systems-II, vol.

[3] D.A.Johns and K. Martin, "Analog Integrated Circuit