應用於電力線通訊系統之高速電流引導式數位類比轉換器

A High Speed Current-Steering DAC for Powerline Communication System

程韋盛(Wei-Sheng Cheng)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.03150

摘要

本論文提出一個適用於高速通訊系統的十位元數位類比轉換器。此數位類比轉換器應用於電力線通訊之類比前端接收發器中的傳送器，並達到電力線網路聯盟之最新規格(HomePlug AV2)。此外，本設計同時與線驅動器整合於系統晶片中。
為了改善靜態表現，我們使用6-4分段分時的編碼架構來達到良好匹配同時降低資料轉換時的突波。此外，我們亦使用四象限對稱方式來完成電流源陣列的設計；並加入假電晶體於陣列邊緣，降低位於陣列中心與邊緣之電流源間的誤差。針對動態表現方面，我們使用數位隨機歸零的技巧[10][11]來達到高速取樣頻率時的效能。
本晶片使用台積電90奈米互補式金氧半製程，晶片主動區域面積約0.42mm2。數位電路的電壓供應為1.2-V，類比電路的電壓供給為2.5-V。最大的積分非線性誤差(INL)為0.8-LSB，最大的微分非線性誤差(DNL)為0.3-LSB。無雜散動態範圍(SFDR)在1.25GS/s之Nyquist取樣下都大於40dB。整體功率消耗為58mW。

關鍵字

電流引導式數位類比轉換器 ； 電力線通訊

並列摘要

A 10-bit current-steering digital-to-analog converter (DAC) has been proposed for high speed communication systems. This study is used for the transmitter (Tx) of the powerline communication (PLC) analog-front-end (AFE), and it reaches the standard of the HomePlug AV2. And the DAC has also been combined with the line driver as the transmitter of the whole system.
In order to improve static performance, we use 6-4 segmented decoding architecture to get good matching and reduce the glitch. Furthermore, we implemented our current source array as common centroid type and adding dummy current sources around the array to reduce the mismatch between edge and center. For dynamic performance consideration, the proposed DAC uses a technique as digital random-return-to-zero (DRRZ) [10][11] to achieve good performance for high speed sampling frequency.
The test chip was fabricated in TSMC 90 nm CMOS technology and occupied 0.42 mm2 for active area. The supplies for the analog and digital circuits are 2.5V and 1.2V. The maximum INL and DNL are 0.8 LSB and 0.3 LSB respectively. The SFDR is up to 40.09 dB for 1.25GS/s of Nyquist-rate sampling. The power consumption is 58mW.

並列關鍵字

Current-Steering DAC ； Powerline Communication (PLC)

參考文獻

[2] The Data Conversion Handbook, Analog Devices, Inc., 2004

[3] A. van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315-324, Mar. 2001.

[4] Chi-Hung Lin and Klaas Bult, “A 10-b, 500-MSample/s CMOS in 0.6 mm2,” IEEE J. Solid-State Circuits, vol. 33, no. 12, Dec. 1998

[5] A. Van den Bosch, M. Steyaert, and W. Sansen, “An accurate statistical yield model for CMOS current-steering D/A converters,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May 2000, pp. IV.105-IV.108.

[6] J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12-bit intrinsic accuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits, vol. 33, pp. 1959-1969, Dec. 1998.