應用於高解析度影像之管線式類比數位轉換器

A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER

林嘉慶(Chia-ching Lin)

指導教授 ： 蔡明傑

大同大學/電機資訊學院/電機工程學系所/碩士(2010年)

摘要

高解析的視訊在生活中已是不可或缺，尤其是1080P高解析度對於數位電視已為家庭生活上普遍的需求。在類比數位轉換器架構中，管線式類比數位轉換器是最適合應用在中/高速和解析度， 因此本論文對於應用於視訊中類比轉數位規格有詳細的分析， 並且實現一個適用於高解析度的類比數位轉換器。
本篇論文提出十位元，操作頻率在每秒取樣200MHz，第一級採用合併取樣技術輸出一個位元， 後面七級解析一點五位元， 最後一級解析出兩位元的管線式類比數位轉換器，整體電路採用全差動的架構來降低雜訊干擾，為了達到低消耗功率及較小的佈局面積，本論文結合運算放大器共用。電路與結果方面，製程參數是使用TSMC 0.18μm 1P6M互補式金氧半製程，在輸入頻率為75MHz的正弦波輸入下，訊號雜訊失真比為56.6 dB，有效位元為九點一,整體電路消耗功率為73mW

關鍵字

運算放大器共用技術 ； 高解析度 ； 合併取樣技術 ； 管線式類比數位轉換器

並列摘要

The thesis describes the implementation of a 10-bit 200Msampe/s pipelined A/D converter with merged-mode sample and hold circuit which is built in comparator and decoder. The advantage of this architecture is to reduce the signal swing requirement, thus, it enables the use of single -stage cascade amplifier. In addition, it produces the first bit from this sample and hold circuit to reduce one stage sub-ADC. In order to reduce power dissipation, opamp-sharing technique is implemented as well.
Based on result of simulation by HSPICE, this ADC achieves 9.1 bits ENOB at 75MHz, DNL -0.48~+0.5LSB and -0.7LSB~+0.75LSB with power supply 1.8V and 200MHz sampling rate, the overall power dissipation is 73mW and FOM is 0.66 pJ/conversion. Total active area is 0.994 x 0.854 mm2 in 1P6M 0.18μm CMOS process

並列關鍵字

analog to digital ； merged mode ； Opamp-sharing technique ； high definition.

參考文獻

[1] H. Xing, D. Chen, R. Geiger and L. Jin, “System Identification -Based Reduced-Code Testing for Pipeline ADCs’ Linearity Test,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 2402-2405, May 2008.

[3] A. Zjajo, H. Van der Ploeg, and M. Vertreget “A 1.8V 100mW 12-bits 80Msample/s Two-Step ADC in 0.18-um CMOS,” IEEE Journal of Solid-State Circuits, pp.241-244, Jan. 2004

[4] B. G. Lee, B. M. Min, G. Manganaro, and J. W. Valvano, “A 14-b 100-MS/s Pipelined ADC with a Merged SHA and First MDAC,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2613-2619, Dec. 2008.

[6] S. Jiang, M. A. Do, and K. S. Yeo, “An 8-bit 200MSample/s Pipelined ADC with a Mixed-Mode Front-End S/H Circuit,” IEEE Transaction on Circuits and Systems-I: regular paper, vol. 55, no. 6, pp. 1300-1440, Jul. 2008

[7] B. M. Min, P. Kim, F. W. Bowman, D. M. Boisvert, and A. J. Aude, “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2031-2039, Dec. 2003.