管線式類比數位轉換器之研究

Study on Pipelined Analog-to-Digital Converter

陳韋廷(Wei-Ting Chen)

指導教授 ： 盧志文

國立暨南國際大學/科技學院/電機工程學系/碩士(2009年)

摘要

本論文利用TSMC 0.35um 2P4M Mixed Signal 與TSMC 0.18um 1P6M Mixed Signal的製程設計一個10位元管線式類比數位轉換器，其取樣頻率分別為50MHz 與 100MHz，使用電源供給電壓分別為3.3V 與1.8V。其架構為九階段(Stage)的管線式類比數位轉換器，前八個階段採用1.5-bit/stage的技術，最後一個階段則為一個2-bit的快閃式類比數位轉換器。取樣電路(S/H)與DAC/減法器/增益級(MDAC)使用開關式電容電路來完成，在取樣保持電路最前端的輸入開關使用拔靴帶式(Bootstrapped)開關電路讓開關的非線性問題降低。最後在所有級數的輸出經由數位錯誤修正電路而得到十位元的數位輸出碼。整體電路的設計採用全差動的架構來降低雜訊的干擾。
依據Hspice模擬結果，整個管線式類比數位轉換器可操作在50MHz 與 100MHz之取樣頻率，在1MHz之輸入頻率下，其訊號雜訊失真比分別為60.49dB 與 61.06dB，有效位元數分別為9.76位元 與9.85位元，總消耗功率分別為246.09mW與91.06mW。

關鍵字

管線式類比數位轉換器 ； 1.5-bit/stage ； 數位錯誤修正電路訊號雜訊失真比 ； 有效位元數

並列摘要

In this thesis, we design a 10-bit 50MHz and a 10-bit 100MHz pipelined analog-to-digital converters with TSMC 0.35um 2P4M mixed signal process technology at 3.3V supply voltage and TSMC 0.18um 1P6M Mixed Signal process technology at 1.8V power supply voltage, respectively. The ADC architecture consists of nine stages in this design. Particularly, we adopt the 1.5-bit per stage tepology for the first eight stages and a 2-bit flash ADC in the last stage. We adopt switch-capacitor circuit to design the sample and hold circuit (S/H) and the multiplying DAC (MDAC). In order to reduce the nonlinearity of on resistance for the input switch, the bootstrapped switch structure is used to implement the switches of S/H input. Finally, we can get accurate 10-bit digital codes by using digital error correction circuit. Besides, in order to decrease noise effect, the whole circuit is designed by fully differential structure.
According to Hspice simulation results, the designed pipelined ADCs can operate at 50MHz and 100MHz, respectively. The Signal-to-Noise and Distortion Ratio are 60.49dB and 61.06dB when the input frequency is 1MHz, and the effective numbers of bit are 9.76-bit and 9.85-bit. The power dissipation are 246.09mW and 91.06mW.

並列關鍵字

pipelined analog-to-digital converter ； 1.5-bit per stage ； digital error correction circuit ； Signal-to-Noise and Distortion Ratio ； effective number of bit

參考文獻

[1] David A. Johns and Ken Martin, ”Analog Integrated Circuit Design,” John Wiley & Sons, Inc., 1997.

[2] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, ”CMOS Data Converter For Communication,” Kluwer Academic Publishers, Boston, 2002.

[3] Ching-Yuan Yang, ”Data Convert Fundamentals,” 前瞻類比積體電路設計上課講義, National Chung Hsing University, May 2008.

[4] Chuan-Chi Fan, ”Low Power High Speed 8-Bit Pipelined A/D Converter for RGB Image Processing,” Master Thesis, National Chung Cheng University, July 2005.

[5] Wei-Liang Lin, ”Quantization,Static and Spectral Performance Metrics,” 混合訊號積體電路設計上課講義, National Chung Hsing University, May 2008.