無負載管線式類比數位轉換器之設計

Design of a discharge-phase free loading-free pipelined analog-to-digital converter

楊菁華(Ching-Hua Yang)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.10162

摘要

摘要
本論文介紹目前所有無負載的切換架構並提出兩種新穎的無負載切換架構以克服其他架構的缺點。兩個採用所提出無負載架構並結合餘數摺疊的管線式類比數位轉換器已設計於CMOS製程。第一個雛形電路是使用第一種無負載架構並搭配餘數摺疊,實現於0.13μm CMOS製程，運算放大器共享以及相關振幅位移等技術使用於第一個雛形電路；第二個雛形電路使用所提出的兩種無負載切換架構並搭配餘數摺疊，實現於90nm CMOS製程。
依據模擬結果，兩個雛形電路分別可操作在100MHz 與 250MHz之取樣頻率，在nyquist之輸入頻率下，其訊號雜訊失真比分別為57.83dB 與 59.6dB，有效位元數分別為9.31位元 與9.56位元，總消耗功率分別為26mW與48.5mW。

關鍵字

類比數位轉換器 ； 管線式類比數位轉換器 ； 餘數摺疊 ； 無負載 ； CMOS製程

並列摘要

Abstract
This thesis surveys all the loading-free topologies up to date and proposes two loading-free topologies to overcome shortcomings of other topologies.. Two pipelined analog-to-digital converters(ADC) adopting the proposed loading-free topologies with folded residue technique have been implemented in a CMOS technology .The first prototype based on proposed first loading-free topology and folded residue technique is designed in a standard 0.13-μm CMOS process. Op sharing and Correlated Level shifting techniques are employed in the first prototype. The second prototype based on both proposed loading-free topologies and folded residue technique is designed in a standard 90nm CMOS process.
According to Hspice simulation results, the two prototypes can operate at 100MHz and 250MHz, respectively. The Signal-to-Noise and Distortion Ratio are 57.83dB and 59.6dB when the input frequency is nyquist-rated, and the effective numbers of bit are 9.31-bit and 9.56-bit. The power dissipation are 26mW and 48.5mW.

並列關鍵字

ADC ； pipelined ADC ； folded residue ； loading-free ； CMOS process

參考文獻

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