低功率連續漸進式及管線式類比數位轉換器之設計與應用

Design and Application of Low Power Pipelined and SAR Analog-to-Digital Converters

方柏翔(Po-Hsiang Fang)

指導教授 ： 呂學士

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.03048

摘要

無資料

關鍵字

類比數位轉換器 ； 連續漸進式 ； 管線式

並列摘要

As the rapid growth on the development of the wireless communication system, the requirement for the ADC that connect the digital and analog circuits becomes stricter and stricter. In this thesis, two kinds of ADCs are implemented that contain power-saving techniques.
In Chapter 3 of this thesis, a low power SAR ADC is presented which uses the advantage of the fully differential structure to decrease the requirement of capacitors, that makes the chip area smaller while get the same resolution as the traditional circuit. The chip is fabricated by TSMC 0.35um 2P4M CMOS technology and the measurement results will be shown.
In Chapter 4, a pipelined ADC is introduced which uses opamp current reuse technique to decrease the power dissipation without summing node reset problem. As a result, we can get the advantage of pipelined ADC that has high operation speed without massive power consumption.

並列關鍵字

ADC ； SAR ； pipelined

參考文獻

[1] Y. K. Chang et al, “A 8-bit 500-KS/s Low Power SAR ADC for Bio-Medical Applications”, IEEE Asian Solid-State Circuits Conference, November, 2007

[2] Pierangelo Confalonieri , “A 2.7mW l MSps lob Analog-to-Digital Converter with Built-in Reference Buffer and l LSB Accuracy Programmable Input Ranges”, ESSCIRC 2004, pp. 255 - 258, Sept. 2004.

[3] Jun He et al, “A Simple and Accurate Method to Predict Offset Voltage in Dynamic Comparators”, IEEE International Symposium on Circuits and Systems, pp. 1934-1937, May, 2008.

[4] V. K. Randall et al, “A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs”, APCCAS, 2006.

[5] RYU et al, ”A 10-bit 50-MS/s Pipelined ADC with OPAMP Current reuse”, IEEE JSSC, VOL. 42, NO. 3, March, 2007.