合併電容開關式連續漸近式類比數位轉換器之實現與設計

The Design and Implement of Merged Capacitor Switching based SAR ADCs

林重皓(CHUNG-HAO LIN)

指導教授 ： 盧志文

國立清華大學/原子科學院/工程與系統科學系/碩士(2014年)

https://doi.org/10.6843/NTHU.2014.00327

摘要

此篇論文提出詳細的SAR ADCs設計流程，並在時域與頻域上分別討論設計時所需瞭解之電路運作原理，同時利用直觀的方式配合電路模擬軟體完成了整體SAR ADC之設計與佈局。實際設計流程則利用相對於傳統SAR ADC在比較過程上更加省電的合併電容開關式架構分別完成兩顆SAR ADC的設計。十二位元，低速之同步SAR ADC的設計上提出了簡單的數位控制邏輯，並利用低回踢雜訊比較器提升其有效位元數；另外，十位元，中速之非同步SAR ADC的設計上則提出了改良式動態D型暫存器解決了動態D型暫存器在數位邏輯上的錯誤，同時也利用低回踢雜訊比較器降低可能發生之錯誤。
十二位元，低速之同步SAR ADC的全範圍輸入電壓(V_FS)可達2*V_DD的95%，且在奈奎氏取樣率下可得有效位元數9.68，其FoM可達62(fJ/Con.-step)，其他較低之輸入頻率也皆能得到9.7以上的解析度。此外，在同樣量測環境下，各別量測不同晶片可得其有效位元數最低皆可達9.61，證實了製程偏移對於此電路架構的影響並不大。
十位元，中速之非同步SAR ADC的全範圍輸入電壓(V_FS)可達2*V_DD的95%，降速至3MHz後在奈奎氏取樣率下可得有效位元數8.73，其FoM可達88(fJ/Con.-step)，其他輸入頻率也皆能得到8.64以上的解析度。最後，各別量測不同晶片可得其有效位元數最低可達8.66，同時也證實了此晶片的重現性與可靠度。

關鍵字

類比數位轉換器 ； 連續漸進式 ； 合併電容開關式 ； 低回踢雜訊 ； 設計流程

並列摘要

This thesis elaborated a design process of SAR ADCs, which discussed the fundamental circuit theorems in SAR ADCs by aspects of time and frequency domains and meanwhile, completing the layout and the design of whole ADC by the circuit simulation tools with an easy intuition. Relative to the conventional SAR ADC, the merged capacitor switching based SAR ADCs are more power efficient. Therefore, the thesis implemented two SAR ADCs which based on the merged capacitor switching algorism, including a 12-bit 100k-S/s synchronous SAR ADC, which contained a simple digital control logic and a low-kickback noise comparator to enhance the ENOB, and a 10-bit 10M-S/s asynchronous SAR ADC, which modifying the dynamic D type Flip-Flop to avoid the error in asynchronous clock generator and also used a low-kickback noise comparator to decrease the possibility of the wrong comparative process.
The input signal range of the 12-bit 100k-S/s synchronous SAR ADC could achieve 95% of 2V_DD. The ENOB at Nyquist rate is 9.68, and the FoM is 62(fJ/Con.-step). Furthermore, the ENOB at lower frequency input of ADCs could all achieve over 9.7. In the other hand, the ENOB of the other chips at Nyquist rate are all above 9.61, which verified the influence of the process variation in those chips is small.
The input signal range of the 10-bit 10M-S/s asynchronous SAR ADCs could also achieve 95% of 2V_DD. After decreasing the sampling rate to 3M-S/s, the ENOB at Nyquist rate is 8.73, and the FoM is 88(fJ/Con.-step). Furthermore, the ENOB at lower frequency input of ADCs could all achieve over 8.64. In the other hand, the ENOB of the different chips at Nyquist rate are all above 8.66, which proved that the reliable and repeatable of these chips is well.

並列關鍵字

Analog to digital convertor ； Successive approximation registor ； emerged capacitor switching ； low-kickback noise ； Desgin process

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