全數位電容校正的連續漸進式類比至數位轉換器

All Digital Capacitance Calibration for Successive-Approximation Register Analog-to-Digital Converter

林昭輝(Jhao-Huei Lin)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201800266

摘要

本文提出了一個操作在0.7伏特電源電壓每秒一百萬次取樣的十二位元高功率連續漸進式類比數位轉換器。通過使用偵測和迴避演算法，可以降低電容式數位類比轉換器的切換能量。為了更加省電，單位電容可以縮小以大大降低電容式數位類比轉換器切換能量。
當類比數位轉換器採用檢測和迴避演算法來切換電容式數位類比轉換器時，存在一個權重補償的瓶頸。分離式權重補償可以完美地克服這個瓶頸。在校正模式下，可重構冗餘可以解決比較器偏移的問題。另外，電壓共模準位的跟踪切換可以提高解析度以減少校準收斂時間。
所提出的類比數位轉換器是使用40奈米CMOS製成實現。在0.7伏特電源供應下，它以每秒一百萬次取樣的取樣速率消耗2.47瓦特。前景校正後，測得的差動非線性和積分非線性分別為+ 0.61 / -0.57和+ 0.93 / -0.92最低有限位元。量測所測得的訊號對雜訊及諧波比和無雜散動態範圍分別為66.54 dB和89.55 dB。有效位元為10.75 b，這相當於Walden和Schreier品質因數分別為1.47 fJ / conversion-step和179.6 dB。

關鍵字

連續漸進式 ； 類比數位轉換器 ； 數位類比轉換器 ； 偵測和迴避 ； 分離式權重補償 ； 可重構冗餘 ； 電壓共模準位的跟踪切換

並列摘要

This thesis presents a 12-bit 1 MS/s high power-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with 0.7V supply voltage. By using detect-and-skip (DAS) algorithm, the capacitive digital-to-analog converter (DAC) switching power can be reduced. To be more power-efficient, the unit capacitance can shrink to decrease the DAC switching power largely.
There is a bottleneck of weight compensation when the ADC takes the DAS algorithm to switch DAC. The weight-split compensation (WSC) can overcome this bottleneck perfectly. In the calibration mode, the reconfigurable redundancy can resolve the problem of the comparator offset. In addition, the Vcm-based tracking switching can enhance the resolution to decrease the calibration converge time.
The propose ADC is fabricated using a 40-nm CMOS process. It consumes 2.47 W from a 0.7-V supply at a conversion-rate of 1 MS/s. After foreground calibration, the measured DNL and INL are +0.61/-0.57 and +0.93/-0.92 LSB. The measured SNDR and SFDR are at 66.54 dB and 89.55 dB, respectively. The ENOB performance is 10.75 b, which is equivalent to a Walden and Schreier figure-of-merit of 1.47 fJ/conversion-step and 179.6 dB, respectively.

並列關鍵字

Successive-approximation register (SAR) ； analog-to-digital converter (ADC) ； digital-to-analog converter (DAC) ； detect-and-skip (DAS) ； weight-split compensation (WSC) ； reconfigurable redundancy ； Vcm-based tracking switching

參考文獻

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