高速高電能效率的時間交錯式連續漸進式類比至數位轉換器

High-Speed and Energy-Efficient Time-Interleaved SAR ADC

吳世偉(Shih-Wei Wu)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201603693

摘要

近年來，每秒幾億次至十幾億次的中解析度類比至數位轉換器的應用越來越廣泛，以利取代接收端(Receiver)的前端。本論文提出一個以40奈米CMOS一般製程的高速高效能的時間交錯式及子空間連續漸進式類比至數位轉換器，一利用舒緩電容陣列穩定時間的技巧來改進電路整體時間的安排，運用於兩個五位元的Coarse SAR ADC來輔助四個通道的十位元Fine SAR ADC的架構。為了解決時間交錯式類比至數位轉換器的子通道間時脈偏移不匹配問題，提出了一個低時脈偏移的取樣電路，無需額外的校正電路。

本作品的量測結果顯示可操作在每秒十億的轉換及輸入頻率為兩億五千萬赫茲；或每秒五億的轉換與奈奎斯特的輸入頻率之下，SNDR分別為49.51dB和51.45dB。功率消耗為5.899毫瓦跟3.0245毫瓦。並得到優良的品質因數(FoM)為24.15 fJ/c.-s跟19.83 fJ/c.-s。其適合用在高電能效益的無線通訊與乙太網路應用中。

關鍵字

類比至數位轉換器 ； 時間交錯式 ； 連續漸進式 ； 高速 ； 高電能效益 ； 低時脈偏移解多工器 ； 子空間

並列摘要

Recently, hundreds MS/s to 1GS/s medium resolution Analog-to-Digital Convertors (ADCs) are used extensively in applications, for the purpose to replace the front end of the receiver. This thesis proposed a high-speed and energy-efficient time-interleaved subranging SAR ADC that utilizing settling time relief technique [1] to improve overall circuit arrangement by using two 5-bit coarse ADCs to assist 10-bit four channels fine SAR ADC architecture. To solve the problem that skew mismatch within sub-ADCs in subranging architecture, we propose a low-skew bootstrap circuit without additional calibration circuit.
This time-interleaved SAR ADC can achieve the conversion rate of 1GS/s with near 220 MHz input frequency, and 500MS/s with Nyquist rate, SNDR are 49.51 dB and 51.45 dB, respectively. The power consumption is 5.899mW and 3.0245mW, respectively. And, getting the good FoM of 24.15 fJ/c.-s. and 19.83 fJ/c.-s. The active area is 0.0459 mm2. It is suitable for the energy-efficient wireless communication and Ethernet network application.

並列關鍵字

analog-to-digital converter (ADC) ； time-interleaved ； successive-approximation register (SAR) ； high speed ； energy-efficient ； low-skew front-end ； subranging

參考文獻

[1] Y. S. Hu, et al, “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s Subranging SAR ADC in 40nm CMOS,” IEEE ASSCC. Dig. Tech. Papers, pp. 81-84, Nov. 2014.

[2] S. Lee, et al, “A 1GS/s 10b 18.9mW Time-Interleaved SAR ADC with Background Timing-Skew Calibration” IEEE ISSCC Dig. Tech. Papers, vol. 1, pp. 378-379, Feb. 2014.

[3] H. Hong, et al, “An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADC with a 1b/cycle Reconfiguration for Resolution Enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 470-471, Feb. 2013.

[4] D. Stepanovic, et al, “A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS,” IEEE JSSC, vol. 48, no. 4, pp. 971-982, Apr. 2013.

[6] B. D. Sahoo , et al., “A 10-Bit 1-Ghz 33-mW CMOS ADC,” IEEE Symp. VLSI Circuits, 2012, pp. 30–31.