低時脈偏移高速低功率四通道時間交錯連續漸進式類比至數位轉換器

Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC

楊蜜迪(Mi-Ti Yang)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201603695

摘要

由於無線通訊系統的演進，對於高速中解析度的類比至數位轉換器需求日漸增加。本論文提出一個十位元每秒十億次轉換的時間交錯式連續漸進式類比至數位轉換器，以40奈米製程的CMOS呈現。
本論文為了解決時間交錯式類比至數位轉換器的通道間時脈偏移不匹配問題，提出了一個不需要數位校正的低時脈偏移前端取樣電路。子電路使用高電能效率的連續漸進式單通道架構，使整體類比至數位轉換器的品質因數可以降至最低。
　　本時間交錯式連續漸進式類比至數位轉換器在每秒十億次的取樣速度與兩億五千萬赫茲的輸入頻率之下有七點九位元的有效位元，其主動面積只有0.0459mm2。功率消耗為3.0245mW，達到一個優異的品質因數為19.83 fJ/conversion-step，其適合用在高電能效益的無線通訊與乙太網路應用中。

關鍵字

類比至數位轉換器 ； 時間交錯式 ； 連續漸進式 ； 高速 ； 高電能效益 ； 低時脈偏移

並列摘要

As the advantage of wireless communication system, the requirement for high speed sampling rate and medium resolution gradually increase. A 10-bit 1GS/s time-interleaved SAR ADC is presented in 40nm general process of CMOS technology in this thesis.
This thesis proposes a low-skew bootstrap to solve the timing skew problem between channels without digital calibration. In order to improve the energy-efficiency of the sub-channel, the subranging SAR ADC is used for lowing the FOM.
This time-interleaved SAR ADC achieves an ENOB of 7.9 at the conversion rate of 1GS/s with 250MHz input signal. The active area is only 0.0459 mm2. It consumes 3.0245mW and gets the good FoM of 19.83fJ/conversion-step. It is suitable for the energy-efficient wireless communication and Ethernet network application.

並列關鍵字

analog-to-digital converter (ADC) ； time-interleaved ； successive-approximation register (SAR) ； high speed ； energy-efficient ； low-skew

參考文獻

[1] N. Le Dortz, "A 1.62 GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70 dBFS", IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 386-388

[2] I. N. Ku, Z. Xu, Y. C. Kuan, Y. H. Wang and M. C. F. Chang, "A 40-mW 7-bit 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communications", IEEE J. Solid-State Circuits, vol. 47, no. 8, pp. 1854-1865, Aug. 2012.

[3] S. Lee, A. P. Chandrakasan and H-S. Lee, "A 1 GS/s 10 b 18.9 mW time-interleaved SAR ADC with background timing skew calibration", IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2846-2856, 2014

[4] H.-K. Hong, H.-W. Kang, B. Sung, C.-H. Lee, Michael Choi, H.-J. Park and S.-T. Ryu, “An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADC with a 1b/cycle Reconfiguration for Resolution Enhancement,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 470-472, Feb. 2013

[5] D. Stepanovic and B. Nikolic, “A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 971–982, Apr. 2013