類比數位轉換器及數位類比轉換器之設計與應用

在本論文的第三章，我們將介紹一個解析度為六位元，轉換頻率為一百萬赫茲的電容切換式數位類比轉換器。此轉換器將整合在神經刺激器裡，作為一任意波型產生器，以提供不僅止於方波的刺激波形。在第四章，我們將介紹一個解析度十位元，轉換頻率為一百萬赫茲的數位類比轉換器。此轉換器使用我們所新提出的電容電阻混合式架構，相較於其他傳統架構可在較少面積和功率消耗之下達到高解析度。第五章將介紹一個解析度十位元，轉換頻率為五十百萬赫茲的管線式類比數位轉換器。利用電流重複運用的技巧，和傳統管線式架構相比可減少約一半的類比功率消耗。本論文裡的所有晶片皆使用TSMC 2P4M 0.35μm CMOS的製程來設計和實現。

關鍵字

數位類比轉換器；類比數位轉換器；電容切換式；混合式；管線式

並列摘要

In Chapter 3, a 6-bit, 1MHz, low power DAC is presented. This chip is designed to be an arbitrary waveform generator for the neural stimulator. In Chapter 4, a 10-bit, 1MHz, low power DAC using the proposed “C-R hybrid architecture” is presented. With this architecture, the DAC can achieve high resolution while using lower power and smaller area comparing with other architecture. In Chapter 5, a 10-bit, 50MHz, pipelined ADC is presented. By using the “opamp current reuse technique”, the analog power consumption is reduced by half comparing with the conventional pipelined ADC. All chips in this thesis are designed and fabricated using TSMC 2P4M 0.35μm CMOS technology.

並列關鍵字

DAC ； ADC ； Switched-Capacitor ； Hybrid ； Pipelined

參考文獻

[2] 莊勝富, “Layout of a Resistor-String Successive Reference Generator”, July 2007.

[3] Che-Wei Chang, “Design and Application of Analog-to-Digital Converter”, July 2007.

[4] Seung-Tak Ryu, Bang-Sup Song, and Kantilal Bacrania, “A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 3, MARCH 2007

[6] Chunlei Shi, Mohammed Ismail, “Data Converters for Wireless Standards”, 2001.

[7] Franco Maloberti, “Data Converters”, 2007.

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類比數位轉換器及數位類比轉換器之設計與應用

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