功率效率化之類比數位轉換器設計與分析

隨著積體電路製程持續進步，供給電壓與電晶體體積急速減小，數位電路的運算能力也不斷增加。但對類比電路而言，較低的供給電壓與相對較大的臨界電壓，反而造成了電路設計上的困難。類比數位轉換器連結了類比世界與數位電路。由於在他的使用上延伸了純類比信號與類比數位混和信號的運作，類比數位轉換器往往成為了資料運算應用上的瓶頸，限制了整個系統的速度與精確度。由於輕便性與系統單晶片整合的需求持續增加，低功率消耗與深次微米製程的相容性均成為當今類比類為轉換器的重要設計考量。在系統單晶片的實現上，資料轉換器往往與威力強大的數位訊號處理系統整合在同一顆單晶片內，造成了整體設計上熱能與功率消耗的限制。在這篇論文中，一個五位元快閃式類比數位轉換器被用以電容式陣列數位類比轉換器實現。電容式陣列數位類比轉換器在轉換層級上提供了功率效率化。在量測方面，本設計使用0.18微米製程，功率消耗在2百萬赫茲時脈速率時，功率消耗非常小。隨著積體電路整合的提升，這個設計可以用在低功率五十億赫茲無線接收機系統。另一方面，一個六位元高速且低功率管線化漸進式類比數位轉換器也被介紹。應用增進化混合式減法器與C-2C架構，這個電路運作在高速與低功率情形下。藉著C-2C架構，這個提出的架構降低了靜態功率消耗藉著電荷重新分配數位類比轉換器以及電容精確度需求。本設計使用0.18微米製程，當類比數位轉換器運作在三億赫茲時脈速率時，僅消耗252毫瓦。

關鍵字

類比數位轉換器；導管化；漸進式

並列摘要

By aggressive device scaling in modern integrated circuit technology, the computing power of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design constraints for analog circuit. Analog-to-digital converters provide the link between the analog world and the digital system. Due to their extensive use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision. For the increasing demand for portability and system-on-a-chip (SoC) integration, low-power dissipation and the compatibility with deep-submicron technology have emerged as important metrics in state-of-the-art ADC design. In SoC implementations, data converters are embedded on the same chip with powerful fine-line digital signal processing, resulting in a limited budget for their total heat and power consumption. In this thesis, a 5-bit flash ADC was implemented by using capacitor-DAC array technique. The capacitor-DAC array provides efficient power strategy in conversion stage design. For the measurement results of the prototype fabricated in TSMC CMOS 0.18-μm 1P6M technology, the power dissipation is extremely low in 2-MHz sampling frequency. With the trend of increasing integration complexity of VLSI circuits, this design is capable of being adopted in the low-power 5-GHz wireless receiver system. On the other hand, a 6-b high speed and low power pipelined successive-approximation ADC is presented. Employing improved-MMS and C-2C architecture, the circuit operates in high speed and low power consumption.. The proposed architecture reduces the static power consumption by charge redistribution digital-to-analog converter and lowers the accuracy requirement of the capacitor in the conventional SA-ADC by the C-2C architecture. Designed in a 0.18-μm technology, the ADC operates at 300-Ms/s clock rate while power dissipation is 252 mW.

並列關鍵字

ADC ； pipelined ； successive-approximation

參考文獻

[1] M. Gustavsson, J..J. Wikner and N.N. Tan, “CMOS Data Converters For Communications,” Kluwer Academic Publisher, 2000.

[2] B. Razavi, “Principles of Data Conversion System Design,” Wiley-IEEE Press, 1995.

[3] K. Uyttenhove, A. Marques and M. Steyaert, “A 6-bit 1 GHz Acquisition Speed CMOS Flash ADC with Digital Error Correction,” IEEE Custom Integrated Circuits Conference, 2000.

[7] D.A. Johs and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997, pp. 517-523.

[8] A.G.W. Venes and R.J. van-de-Plassche, “An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing,” in IEEE Journal of Solid-State Circuits, vol. 31, pp. 1846-1853, Dec. 1996.

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功率效率化之類比數位轉換器設計與分析

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