類比數位轉換器之設計與應用

Design and Application of Analog-to-Digital Converter

張哲維(Che-Wei Chang)

指導教授 ： 呂學士

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.10605

摘要

近年來許多研究致力於實現低功率之無線感測網路，而感測網路的使用壽命取決於感測節點的功率消耗。於本論文的第一部份中，一個適用於感測網路之低功率十位元軌對軌連續逼近式類比數位轉換器將被實現。此類比數位轉位器具備軌對軌的轉換區間，可容納多種類型感測器的應用。利用門閘式時脈、功率開關及直接以供應電壓為參考電壓等技巧，量測結果顯示此晶片操作於一千赫茲轉換速度時，功率消耗僅為1.8uW。操作於十萬赫茲轉換速度，其最高有效位元數超過9.4位元，有效信號頻寬則超過奈奎斯特頻率。微分型非線性誤差介於+ 0.6215/ - 0.7280 最小單位位元，積分型非線性誤差為+0.60 / -0.584最小單位位元。晶片面積為570um x 595um，以TSMC 0.35um CMOS 2P4M製程製作。

另一方面，新的通訊標準已朝向高解析度、高傳輸速率發展，以便能提供更多的服務。此外類比和數位訊號處理的界線也逐漸往天線端靠近；高速高解析度之類比數位轉換器已成為通訊系統中不可或缺的關鍵區塊。本論文的第二部分，一個應用於高速無線傳輸系統之十位元五千萬赫茲管線式類比數位轉換器將被實現。操作電壓為2.7伏特。此類比數位轉換器使用了靴帶式開關、增益增強型運算放大器、翻轉取樣保持電路及其他多種電路技巧以達成高轉換速度。量測結果顯示操作於五千萬赫茲轉換速度，此晶片功率消耗約為135mW。微分型非線性誤差介於+ 0.286 / - 0.264 最小單位位元，積分型非線性誤差為 + 0.490 / - 0.477最小單位位元。於低輸入訊號頻率操作時，最高訊號對雜訊及失真功率比值為55.75dB (8.97有效位元)；操作於奈奎斯特輸入訊號頻率，訊號對雜訊及失真功率比值為53.92dB (8.67有效位元)。晶片面積為1.755mm x 1.585mm, 以TSMC 0.35um CMOS 2P4M製程製作。

關鍵字

類比-數位 ； 類比數位轉換器 ； 管線 ； 導管 ； 連續逼近 ； 連續近似

並列摘要

In recent years, many researches are focused on the implementation of low power wireless sensor networks. The lift time of a wireless sensor network relies on the power dissipation of individual sensor node. In the first part of this thesis, a 10-bit, ultra-low power, successive approximation ADC with rail-to-rail conversion range for wireless sensor network is implemented. This ADC is capable of rail-to-rail conversion range to accommodate multiple types of sensors. By employing techniques such as gating-clock, power switch, and directly using supply voltage as reference voltage, the measurement result shows that this ADC dissipates only 1.8uW at 1KSPS. Operating at 100KSPS, the maximum effective number of bits (ENOB) is higher than 9.4 bits and the effective resolution bandwidth (ERB) is wider than Nyquist band. The measured differential non-linearity (DNL) is between +0.6215/ -0.7280 LSB and the integral non-linearity (INL) is between +0.6015 / -0.5836 LSB. Fabricated in TSMC 0.35um CMOS 2P4M process, the die area is 570um x 595um.

On the other hand, new communication standards have been an evolution towards high resolution and high data rate. Besides, the boundary between analog and digital signal processing is moving toward the antenna. Consequently, an ADC capable of high speed and high resolution becomes more essential in the communication system. In the second part of this thesis, a 2.7V, 10-bit, 50MSPS CMOS pipelined ADC for high speed wireless communication system is implemented. This ADC employed the bootstrapped switch, the gain-boosting operational amplifier, the filp-around SHA and many other circuit techniques to achieve high conversion rate. Operating at 50MSPS, this ADC dissipates 135mW with 2.7V supply voltage. The measured DNL is between +0.286 / - 0.264 LSB and the INL is between +0.490 / -0.477 LSB. The signal-to-noise-and-distortion ratio (SNDR) is 55.75dB (ENOB=8.97 bits) at low input frequency and is 53.92dB (ENOB=8.67 bits) at Nyquist frequency. This chip is implemented in TSMC 0.35um 2P4M CMOS process and the die area is 1.755mm x 1.585mm.

並列關鍵字

Analog-to-Digital Converter ； ADC ； Pipeline ； SAR ； Successive Approximation

參考文獻

[2.4] B. Razavi, “Principles of Data Conversion System Design” IEEE Press 1995

[2.5] 蘇逸霈, “An Analog-to-Digital Converter with DLL Clock Generator,” National Taiwan University MS Thesis, July 2006.

[3.1] Kay Romer and Friedmann Mattern, “The Design Space of Wireless Sensor Networks,” IEEE Wireless Communications, pp. 54-61, December 2004.

[3.2] M. D. Scott, B. E. Boser, and K. S. J. Pister, “An ultralow-energy ADC for smart dust.” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123-1129, Jul. 2003

[3.3] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1-uW successive approximation ADC” IEEE J. Solid-State Circuits, vol. 38, pp. 1261-1265, July, 2003