10位元100MHz管線式類比數位轉換器之設計

Design of a 10-bit 100MHz Pipelined ADC

李修全(Hsiu-Chuan Li)

指導教授 ： 陳淳杰

中原大學/工學院/電子工程研究所/碩士(2014年)

https://doi.org/10.6840/cycu201400485

摘要

以設計一個低功率及小面積的1.5bit/perstage之10位元100MHz管線式類比數位轉換器為目標，整體電路共分為九級，採用運算放大器共享技術，將前八級的運算放大器數量減少至四個，大幅降低面積及功耗。此類比數位轉換器使用TSMC 0.18um 1P6M CMOS製程；當輸入訊號頻率為Nyquist頻率時，其訊號對雜訊失真比為53.3dB、有效位元為8.56，整體功耗為42.6mW，FOM為1.129pJ/conversion。

關鍵字

管線式類比數位轉換器

並列摘要

This paper describes a 10-bit 100Msample/s pipelined analog-to-digital converter (ADC) fabricated in TSMC 0.18um 1P6M CMOS technology. By amplifier sharing technique, the converter is realized using only four amplifiers in front of eight stage to reduce the chip area and power consumption. This converter achieves 53.3-dB signal-to-noise ratio, 8.56 effective number of bits for a Nyquist frequency input at full sampling rate, and consumes 42.6mW from a 1.8-V supply. The FOM is 1.129pJ/conversion.

並列關鍵字

Pipelined ADC

參考文獻

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